Revision 149

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trunk/librairies/polytech_ge_beta/relais_1c_1p/sym_1/symbol.css
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P "CDS_LMAN_SYM_OUTLINE" "-125,150,125,-150" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
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L -125 150 -125 -150 -1 0
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L -125 150 125 150 -1 0
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L 125 150 125 -150 -1 0
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L -125 -150 125 -150 -1 0
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T -21 175 0 0 29 0 0 1 0 11 0
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C 200 50 "7" 225 49 0 1 29 0 L
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X "PIN_TEXT" "7" 140 50 0.00 0.00 23 0 0 2 0 0 1 0 0
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C -150 50 "1" -175 50 0 1 29 0 R
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X "PIN_TEXT" "1" -90 50 0.00 0.00 23 0 0 0 0 0 1 0 0
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C -150 -100 "3" -175 -99 0 1 29 0 R
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X "PIN_TEXT" "3" -90 -100 0.00 0.00 23 0 0 0 0 0 1 0 0
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C 200 -100 "5" 225 -99 0 1 29 0 L
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X "PIN_TEXT" "5" 140 -100 0.00 0.00 23 0 0 2 0 0 1 0 0
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L -50 -75 100 -75 -1 0
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L -50 -75 -50 -125 -1 0
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L 100 -75 100 -125 -1 0
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L 75 -125 100 -75 -1 0
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L -50 -125 100 -125 -1 0
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L -50 -125 -25 -75 -1 0
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L -100 -175 150 -175 -1 0
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L -100 -175 -100 125 -1 0
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L 150 -175 150 125 -1 0
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L -100 125 150 125 -1 0
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L 50 50 200 50 -1 0
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L 0 50 -150 50 -1 0
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L 0 50 50 75 -1 0
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L -150 -100 -50 -100 -1 0
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L 0 -125 25 -75 -1 0
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L -25 -125 0 -75 -1 0
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L 25 -125 50 -75 -1 0
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L 50 -125 75 -75 -1 0
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L 200 -100 100 -100 -1 0
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T 4 150 0.00 0.00 29 0 0 1 0 12 0
7 29
relais_1c_1p
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L -125 75 -25 75 -1 0
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L 25 75 125 75 -1 0
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L -25 75 25 100 -1 0
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L -125 -75 -75 -75 -1 0
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L -75 -50 -75 -100 -1 0
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L -75 -50 75 -50 -1 0
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L 75 -50 75 -100 -1 0
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L 75 -100 -75 -100 -1 0
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L 75 -75 125 -75 -1 0
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L -75 -100 -50 -50 -1 0
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L -50 -100 -25 -50 -1 0
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L -25 -100 0 -50 -1 0
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L 0 -100 25 -50 -1 0
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L 25 -100 50 -50 -1 0
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L 50 -100 75 -50 -1 0
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L -175 75 -125 75 -1 0
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C -175 75 "1" -200 75 0 1 29 0 R
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X "PIN_TEXT" "1" -115 75 0 0 23 0 0 0 0 0 1 0 0
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L -175 -75 -125 -75 -1 0
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C -175 -75 "3" -200 -74 0 1 29 0 R
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X "PIN_TEXT" "3" -115 -75 0 0 23 0 0 0 0 0 1 0 0
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L 175 -75 125 -75 -1 0
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C 175 -75 "5" 200 -74 0 1 29 0 L
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X "PIN_TEXT" "5" 115 -75 0 0 23 0 0 2 0 0 1 0 0
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L 175 75 125 75 -1 0
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C 175 75 "7" 200 74 0 1 29 0 L
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X "PIN_TEXT" "7" 115 75 0 0 23 0 0 2 0 0 1 0 0
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P "CDS_LMAN_SYM_OUTLINE" "-125,150,125,-150" 25 -25 0.00 0.00 22 0 0 0 0 0 0 0 0
trunk/librairies/polytech_ge_beta/relais_1c_1p/entity/verilog.v
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// generated by newgenasym  Wed Sep 29 14:17:48 2010
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// generated by newgenasym  Wed Oct 06 15:51:10 2010
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module relais_1c_1p (\1 , \3 , \5 , \7 );
trunk/librairies/polytech_ge_beta/relais_1c_1p/entity/vhdl.vhd
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-- generated by newgenasym Wed Sep 29 14:17:48 2010
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-- generated by newgenasym Wed Oct 06 15:51:10 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity relais_1c_1p is
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entity RELAIS_1C_1P is
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    port (    
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	\1\:       INOUT  STD_LOGIC;    
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	\3\:       INOUT  STD_LOGIC;    
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	\5\:       INOUT  STD_LOGIC;    
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	\7\:       INOUT  STD_LOGIC);
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end relais_1c_1p;
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end RELAIS_1C_1P;

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