Revision 142 trunk/librairies/polytech_ge_beta/conn_jack_fem/entity/vhdl.vhd

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vhdl.vhd
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-- generated by newgenasym Mon Oct 04 15:24:46 2010
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-- generated by newgenasym Mon Oct 04 16:19:16 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity CONN_JACK_FEM is
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entity conn_jack_fem is
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    port (    
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	MASSE:     INOUT  STD_LOGIC;    
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	MASSE_C:   INOUT  STD_LOGIC;    
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	VALIM:     INOUT  STD_LOGIC);
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end CONN_JACK_FEM;
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end conn_jack_fem;

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