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psd-data / trunk / librairies / polytech_ge_beta / ltsr6_np / entity / verilog.v @ 124

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// generated by newgenasym  Thu Sep 30 15:14:20 2010
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module ltsr6_np (\0v , in1, in2, in3, out1, out2, out3, out_mes, plus, ref);
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    input \0v ;
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    inout in1;
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    inout in2;
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    inout in3;
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    inout out1;
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    inout out2;
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    inout out3;
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    inout out_mes;
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    input plus;
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    inout ref;
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    initial
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        begin
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        end
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endmodule