Revision 124

View differences:

trunk/librairies/polytech_ge_beta/aff_lcd/sym_1/symbol.css
1
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AFF_LCD
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55

  
47
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AFF_LCD
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trunk/librairies/polytech_ge_beta/aff_lcd/sym_2/symbol.css
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AFF_LCD
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trunk/librairies/polytech_ge_beta/clavier_12_touches/sym_1/symbol.css
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clavier_12_touches
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trunk/librairies/polytech_ge_beta/clavier_12_touches/entity/verilog.v
1
// generated by newgenasym  Wed Sep 22 16:51:20 2010
1
// generated by newgenasym  Wed Sep 29 11:12:22 2010
2 2

  
3 3

  
4 4
module clavier_12_touches (c1, c2, c3, l1, l2, l3, l4);
trunk/librairies/polytech_ge_beta/clavier_12_touches/entity/vhdl.vhd
1
-- generated by newgenasym Wed Sep 22 16:51:20 2010
1
-- generated by newgenasym Wed Sep 29 11:12:23 2010
2 2

  
3 3
library ieee;
4 4
use     ieee.std_logic_1164.all;
5 5
use     work.all;
6
entity clavier_12_touches is
6
entity CLAVIER_12_TOUCHES is
7 7
    port (    
8 8
	C1:        INOUT  STD_LOGIC;    
9 9
	C2:        INOUT  STD_LOGIC;    
......
12 12
	L2:        INOUT  STD_LOGIC;    
13 13
	L3:        INOUT  STD_LOGIC;    
14 14
	L4:        INOUT  STD_LOGIC);
15
end clavier_12_touches;
15
end CLAVIER_12_TOUCHES;
trunk/librairies/polytech_ge_beta/ltsr6_np/metadata/pinlist.txt
16 16
		(CheckOutput 0)
17 17
		(UnknownLoading 0)
18 18
		(PinShape )
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
19 21
	)
20 22

  
21 23
	(Pin
......
35 37
		(CheckOutput 0)
36 38
		(UnknownLoading 0)
37 39
		(PinShape )
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
38 42
	)
39 43

  
40 44
	(Pin
......
54 58
		(CheckOutput 0)
55 59
		(UnknownLoading 0)
56 60
		(PinShape )
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
57 63
	)
58 64

  
59 65
	(Pin
......
73 79
		(CheckOutput 0)
74 80
		(UnknownLoading 0)
75 81
		(PinShape )
82
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	(Pin
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		(UnknownLoading 0)
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		(DIFF_PAIR_PINS_POS )
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	)
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116 128
	(Pin
......
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		(CheckOutput 0)
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		(UnknownLoading 0)
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		(PinShape )
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		(DIFF_PAIR_PINS_POS )
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		(DIFF_PAIR_PINS_NEG )
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	)
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135 149
	(Pin
......
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		(CheckOutput 0)
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		(UnknownLoading 0)
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		(PinShape )
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		(DIFF_PAIR_PINS_POS )
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		(DIFF_PAIR_PINS_NEG )
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	)
153 169

  
154 170
	(Pin
......
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		(CheckOutput 0)
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		(UnknownLoading 0)
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		(PinShape )
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		(DIFF_PAIR_PINS_POS )
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		(DIFF_PAIR_PINS_NEG )
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	)
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173 191
	(Pin
......
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		(CheckOutput 0)
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		(UnknownLoading 0)
189 207
		(PinShape )
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		(DIFF_PAIR_PINS_POS )
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	)
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192 212

  
trunk/librairies/polytech_ge_beta/ltsr6_np/metadata/revision.dat
4 4

  
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		(Baselined	0)
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		(Revision	0.0.3)
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......
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		(LastModifyInfo	
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			(Time	10/03/07,14:03:57)
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			(Time	09/30/10,15:14:19)
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29
			(User	projets)
29
			(User	profs)
30 30

  
31
			(Path	etudiants.ltsr6_np)
31
			(Path	_polytech_ge_beta.ltsr6_np)
32 32

  
33 33
		)
34 34

  
......
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41 41
			(Symbols	2
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				(Symbol	sym_1
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						(ModificationStatus	NULL)
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......
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						(CreateInfo	
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							(Time	10/03/07,14:01:42)
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							(Time	10/03/07,14:03:56)
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......
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				)
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						(ModificationStatus	NULL)
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						(CreateInfo	
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							(Time	10/03/07,14:03:56)
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							(Time	10/03/07,14:01:42)
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							(User	projets)
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		)
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		(View	Chips
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			(Checksum	0000000011341120)
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			(Checksum	00000000c331cc6e)
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			(Primitives	1
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				(Primitive	LTSR6_NP
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......
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									(Linkage	Symbol
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										(Name	sym_2)
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									)
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									(Linkage	Symbol
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										(Name	sym_1)
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									)
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								)
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							)
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						)
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						(Linkages	
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							(DefaultFootPrint	
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								(Name	E_LTSR6)
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							)
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						)
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					)
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				)
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				(Primitive	LTSR6_NP_1_LTRS6_NPV
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							(Time	09/30/10,14:56:12)
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					(LogicalPhysicalPartRelation	
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						(LogicalPart	LTSR6_NP_1
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							)
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trunk/librairies/polytech_ge_beta/ltsr6_np/chips/chips.prt
91 91
  end_body;
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end_primitive;
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94
primitive 'LTSR6_NP_1_LTRS6_NPV';
95
  pin
96
    'IN1':
97
      PIN_NUMBER='(4)';
98
      PIN_TYPE='ANALOG';
99
      NO_LOAD_CHECK='Both';
100
      NO_IO_CHECK='Both';
101
      NO_ASSERT_CHECK='TRUE';
102
      NO_DIR_CHECK='TRUE';
103
      ALLOW_CONNECT='TRUE';
104
    'IN2':
105
      PIN_NUMBER='(5)';
106
      PIN_TYPE='ANALOG';
107
      NO_LOAD_CHECK='Both';
108
      NO_IO_CHECK='Both';
109
      NO_ASSERT_CHECK='TRUE';
110
      NO_DIR_CHECK='TRUE';
111
      ALLOW_CONNECT='TRUE';
112
    'IN3':
113
      PIN_NUMBER='(6)';
114
      PIN_TYPE='ANALOG';
115
      NO_LOAD_CHECK='Both';
116
      NO_IO_CHECK='Both';
117
      NO_ASSERT_CHECK='TRUE';
118
      NO_DIR_CHECK='TRUE';
119
      ALLOW_CONNECT='TRUE';
120
    'OUT3':
121
      PIN_NUMBER='(3)';
122
      PIN_TYPE='ANALOG';
123
      NO_LOAD_CHECK='Both';
124
      NO_IO_CHECK='Both';
125
      NO_ASSERT_CHECK='TRUE';
126
      NO_DIR_CHECK='TRUE';
127
      ALLOW_CONNECT='TRUE';
128
    'OUT2':
129
      PIN_NUMBER='(2)';
130
      PIN_TYPE='ANALOG';
131
      NO_LOAD_CHECK='Both';
132
      NO_IO_CHECK='Both';
133
      NO_ASSERT_CHECK='TRUE';
134
      NO_DIR_CHECK='TRUE';
135
      ALLOW_CONNECT='TRUE';
136
    'OUT1':
137
      PIN_NUMBER='(1)';
138
      PIN_TYPE='ANALOG';
139
      NO_LOAD_CHECK='Both';
140
      NO_IO_CHECK='Both';
141
      NO_ASSERT_CHECK='TRUE';
142
      NO_DIR_CHECK='TRUE';
143
      ALLOW_CONNECT='TRUE';
144
    'REF':
145
      PIN_NUMBER='(7)';
146
      PIN_TYPE='ANALOG';
147
      NO_LOAD_CHECK='Both';
148
      NO_IO_CHECK='Both';
149
      NO_ASSERT_CHECK='TRUE';
150
      NO_DIR_CHECK='TRUE';
151
      ALLOW_CONNECT='TRUE';
152
    '0V':
153
      PIN_NUMBER='(9)';
154
      PINUSE='GROUND';
155
      NO_LOAD_CHECK='Both';
156
      NO_IO_CHECK='Both';
157
      NO_ASSERT_CHECK='TRUE';
158
      NO_DIR_CHECK='TRUE';
159
      ALLOW_CONNECT='TRUE';
160
    'OUT_MES':
161
      PIN_NUMBER='(8)';
162
      PIN_TYPE='ANALOG';
163
      NO_LOAD_CHECK='Both';
164
      NO_IO_CHECK='Both';
165
      NO_ASSERT_CHECK='TRUE';
166
      NO_DIR_CHECK='TRUE';
167
      ALLOW_CONNECT='TRUE';
168
    'PLUS':
169
      PIN_NUMBER='(10)';
170
      PINUSE='POWER';
171
      NO_LOAD_CHECK='Both';
172
      NO_IO_CHECK='Both';
173
      NO_ASSERT_CHECK='TRUE';
174
      NO_DIR_CHECK='TRUE';
175
      ALLOW_CONNECT='TRUE';
176
  end_pin;
177
  body
178
    PART_NAME='LTSR6_NP_1';
179
    BODY_NAME='LTSR6_NP';
180
    JEDEC_TYPE='ltsr_6_npv';
181
    PHYS_DES_PREFIX='U';
182
    CLASS='IC';
183
  end_body;
184
end_primitive;
185

  
94 186
END.
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trunk/librairies/polytech_ge_beta/ltsr6_np/entity/master.tag
1
vhdl.vhd
2 1
verilog.v
trunk/librairies/polytech_ge_beta/ltsr6_np/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Oct  3, 2007  14:03:57
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 30, 2010  15:14:20
trunk/librairies/polytech_ge_beta/ltsr6_np/entity/verilog.v
1
// generated by newgenasym  Wed Oct 03 14:39:26 2007
1
// generated by newgenasym  Thu Sep 30 15:14:20 2010
2 2

  
3 3

  
4 4
module ltsr6_np (\0v , in1, in2, in3, out1, out2, out3, out_mes, plus, ref);
trunk/librairies/polytech_ge_beta/ltsr6_np/entity/vhdl.vhd
1
-- generated by newgenasym Wed Oct 03 14:39:26 2007
1
-- generated by newgenasym Thu Sep 30 15:14:20 2010
2 2

  
3 3
library ieee;
4 4
use     ieee.std_logic_1164.all;
5 5
use     work.all;
6
entity LTSR6_NP is
6
entity ltsr6_np is
7 7
    port (    
8 8
	\0v\:      IN     STD_LOGIC;    
9 9
	IN1:       INOUT  STD_LOGIC;    
......
15 15
	OUT_MES:   INOUT  STD_LOGIC;    
16 16
	PLUS:      IN     STD_LOGIC;    
17 17
	REF:       INOUT  STD_LOGIC);
18
end LTSR6_NP;
18
end ltsr6_np;
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Also available in: Unified diff