Revision 110

View differences:

trunk/librairies/polytech_ge/tel_5/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name VCC1)
4
		(MSB )
5
		(LSB )
6
		(Type INPUT)
7
		(Location Left)
8
		(InputLoadLow -0.01)
9
		(InputLoadHigh 0.01)
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Both)
13
		(CheckIO Both)
14
		(CheckDir 1)
15
		(CheckAssert 1)
16
		(CheckOutput 1)
17
		(UnknownLoading 0)
18
		(PinShape )
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23
	(Pin
24
		(Name COM1)
25
		(MSB )
26
		(LSB )
27
		(Type OUTPUT)
28
		(Location Right)
29
		(InputLoadLow )
30
		(InputLoadHigh )
31
		(OutputLoadLow 1.0)
32
		(OutputLoadHigh -1.0)
33
		(CheckLoad Both)
34
		(CheckIO Both)
35
		(CheckDir 1)
36
		(CheckAssert 1)
37
		(CheckOutput 1)
38
		(UnknownLoading 0)
39
		(PinShape )
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name V+)
46
		(MSB )
47
		(LSB )
48
		(Type OUTPUT)
49
		(Location Right)
50
		(InputLoadLow )
51
		(InputLoadHigh )
52
		(OutputLoadLow 1.0)
53
		(OutputLoadHigh -1.0)
54
		(CheckLoad Both)
55
		(CheckIO Both)
56
		(CheckDir 1)
57
		(CheckAssert 1)
58
		(CheckOutput 1)
59
		(UnknownLoading 0)
60
		(PinShape )
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
63
	)
64

  
65
	(Pin
66
		(Name V-)
67
		(MSB )
68
		(LSB )
69
		(Type OUTPUT)
70
		(Location Right)
71
		(InputLoadLow )
72
		(InputLoadHigh )
73
		(OutputLoadLow 1.0)
74
		(OutputLoadHigh -1.0)
75
		(CheckLoad Both)
76
		(CheckIO Both)
77
		(CheckDir 1)
78
		(CheckAssert 1)
79
		(CheckOutput 1)
80
		(UnknownLoading 0)
81
		(PinShape )
82
		(DIFF_PAIR_PINS_POS )
83
		(DIFF_PAIR_PINS_NEG )
84
	)
85

  
86
	(Pin
87
		(Name COM2)
88
		(MSB )
89
		(LSB )
90
		(Type OUTPUT)
91
		(Location Right)
92
		(InputLoadLow )
93
		(InputLoadHigh )
94
		(OutputLoadLow 1.0)
95
		(OutputLoadHigh -1.0)
96
		(CheckLoad Both)
97
		(CheckIO Both)
98
		(CheckDir 1)
99
		(CheckAssert 1)
100
		(CheckOutput 1)
101
		(UnknownLoading 0)
102
		(PinShape )
103
		(DIFF_PAIR_PINS_POS )
104
		(DIFF_PAIR_PINS_NEG )
105
	)
106

  
107
	(Pin
108
		(Name VCC2)
109
		(MSB )
110
		(LSB )
111
		(Type INPUT)
112
		(Location Left)
113
		(InputLoadLow -0.01)
114
		(InputLoadHigh 0.01)
115
		(OutputLoadLow )
116
		(OutputLoadHigh )
117
		(CheckLoad Both)
118
		(CheckIO Both)
119
		(CheckDir 1)
120
		(CheckAssert 1)
121
		(CheckOutput 1)
122
		(UnknownLoading 0)
123
		(PinShape )
124
		(DIFF_PAIR_PINS_POS )
125
		(DIFF_PAIR_PINS_NEG )
126
	)
127

  
128
	(Pin
129
		(Name GND1)
130
		(MSB )
131
		(LSB )
132
		(Type INPUT)
133
		(Location Left)
134
		(InputLoadLow -0.01)
135
		(InputLoadHigh 0.01)
136
		(OutputLoadLow )
137
		(OutputLoadHigh )
138
		(CheckLoad Both)
139
		(CheckIO Both)
140
		(CheckDir 1)
141
		(CheckAssert 1)
142
		(CheckOutput 1)
143
		(UnknownLoading 0)
144
		(PinShape )
145
		(DIFF_PAIR_PINS_POS )
146
		(DIFF_PAIR_PINS_NEG )
147
	)
148

  
149
	(Pin
150
		(Name GND2)
151
		(MSB )
152
		(LSB )
153
		(Type INPUT)
154
		(Location Left)
155
		(InputLoadLow -0.01)
156
		(InputLoadHigh 0.01)
157
		(OutputLoadLow )
158
		(OutputLoadHigh )
159
		(CheckLoad Both)
160
		(CheckIO Both)
161
		(CheckDir 1)
162
		(CheckAssert 1)
163
		(CheckOutput 1)
164
		(UnknownLoading 0)
165
		(PinShape )
166
		(DIFF_PAIR_PINS_POS )
167
		(DIFF_PAIR_PINS_NEG )
168
	)
169

  
170

  
171
)
trunk/librairies/polytech_ge/tel_5/metadata/master.tag
1
revision.dat
trunk/librairies/polytech_ge/tel_5/metadata/revision.dat
1
(Cell	tel_5
2

  
3
	(RevisionInfoBlock	
4

  
5
		(Baselined	0)
6

  
7
		(Revision	0.0.1)
8

  
9
		(ModificationStatus	NULL)
10

  
11
		(Status	Created)
12

  
13
		(ErrorStatus	0)
14

  
15
		(CreateInfo	
16

  
17
			(Time	09/29/10,11:17:18)
18

  
19
			(User	spinnete)
20

  
21
			(Path	polytech_ge.tel_5)
22

  
23
		)
24

  
25
	)
26

  
27
	(Views	
28

  
29
		(View	Symbol
30

  
31
			(Symbols	1
32

  
33
				(Symbol	sym_1
34

  
35
					(Symbol_Type	Normal)
36

  
37
					(Max_Size	0)
38

  
39
					(Checksum	000000007c32f3b9)
40

  
41
					(RevisionInfoBlock	
42

  
43
						(Baselined	0)
44

  
45
						(Revision	0.0.1)
46

  
47
						(ModificationStatus	NULL)
48

  
49
						(Status	Created)
50

  
51
						(ErrorStatus	0)
52

  
53
						(CreateInfo	
54

  
55
							(Time	09/29/10,11:17:18)
56

  
57
							(User	spinnete)
58

  
59
							(Path	polytech_ge.tel_5)
60

  
61
						)
62

  
63
					)
64

  
65
				)
66

  
67
			)
68

  
69
			(Checksum	000000001c9703b4)
70

  
71
		)
72

  
73
		(View	Chips
74

  
75
			(Checksum	00000000435aab02)
76

  
77
			(Primitives	1
78

  
79
				(Primitive	tel_5_THRU
80

  
81
					(RevisionInfoBlock	
82

  
83
						(Baselined	0)
84

  
85
						(Revision	0.0.1)
86

  
87
						(ModificationStatus	NULL)
88

  
89
						(Status	Created)
90

  
91
						(ErrorStatus	0)
92

  
93
						(CreateInfo	
94

  
95
							(Time	09/29/10,11:17:18)
96

  
97
							(User	spinnete)
98

  
99
							(Path	polytech_ge.tel_5)
100

  
101
						)
102

  
103
					)
104

  
105
					(LogicalPhysicalPartRelation	
106

  
107
						(LogicalPart	tel_5
108

  
109
							(PackType	tel_5_THRU)
110

  
111
						)
112

  
113
					)
114

  
115
					(Packages	1
116

  
117
						(FunctionGroups	1
118

  
119
							(FunctionGroup	1[1]
120

  
121
								(Linkages	
122

  
123
									(Linkage	Symbol
124

  
125
										(Name	sym_1)
126

  
127
									)
128

  
129
								)
130

  
131
							)
132

  
133
						)
134

  
135
						(Linkages	
136

  
137
							(DefaultFootPrint	
138

  
139
								(Name	TEN5)
140

  
141
							)
142

  
143
						)
144

  
145
					)
146

  
147
				)
148

  
149
			)
150

  
151
		)
152

  
153
		(Checksum	000000001e480411)
154

  
155
	)
156

  
157
	(VersionInfoBlock	
158

  
159
		(ToolName	PDV)
160

  
161
		(Version	16.01-s021 (v16-1-53AR))
162

  
163
		(License	PCB_design_expert)
164

  
165
	)
166

  
167
	(Checksum	000000001b5a0349)
168

  
169
)
170

  
trunk/librairies/polytech_ge/tel_5/chips/master.tag
1
chips.prt
trunk/librairies/polytech_ge/tel_5/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'TEL_5_THRU';
3
  pin
4
    'GND1':
5
      PIN_NUMBER='(2)';
6
      INPUT_LOAD='(-0.01,0.01)';
7
    'GND2':
8
      PIN_NUMBER='(3)';
9
      INPUT_LOAD='(-0.01,0.01)';
10
    'VCC1':
11
      PIN_NUMBER='(23)';
12
      INPUT_LOAD='(-0.01,0.01)';
13
    'VCC2':
14
      PIN_NUMBER='(22)';
15
      INPUT_LOAD='(-0.01,0.01)';
16
    'V+':
17
      PIN_NUMBER='(14)';
18
      OUTPUT_LOAD='(1.0,-1.0)';
19
    'V-':
20
      PIN_NUMBER='(11)';
21
      OUTPUT_LOAD='(1.0,-1.0)';
22
    'COM1':
23
      PIN_NUMBER='(9)';
24
      OUTPUT_LOAD='(1.0,-1.0)';
25
    'COM2':
26
      PIN_NUMBER='(16)';
27
      OUTPUT_LOAD='(1.0,-1.0)';
28
  end_pin;
29
  body
30
    PART_NAME='tel_5';
31
    BODY_NAME='TEL_5';
32
    JEDEC_TYPE='TEN5';
33
    PHYS_DES_PREFIX='U';
34
    CLASS='IC';
35
  end_body;
36
end_primitive;
37

  
38
END.
trunk/librairies/polytech_ge/tel_5/sym_1/master.tag
1
symbol.css
trunk/librairies/polytech_ge/tel_5/sym_1/symbol.css
1
P "CDS_LMAN_SYM_OUTLINE" "-150,150,150,-150" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
2
L -150 150 150 150 -1 0
3
L -150 150 -150 -150 -1 0
4
L 150 150 150 -150 -1 0
5
L -150 -150 150 -150 -1 0
6
P "$LOCATION" "?" -124 158 0 0 35 0 0 1 0 0 1 0 0
7
P "NEEDS_NO_SIZE" "TRUE" 25 75 0 0 22 0 0 0 0 0 0 0 0
8
P "PATH" "?" 25 25 0 0 22 0 0 0 0 0 0 0 0
9
P "PART_NAME" "tel_5" 96 159 0 0 22 0 0 1 0 0 1 0 0
10
P "PACK_TYPE" "THRU" 0 0 0 0 22 0 0 0 0 0 0 0 0
11
L -200 100 -150 100 -1 0
12
C -200 100 "VCC1" -222 100 0 1 22 0 R
13
X "PIN_TEXT" "VCC1" -138 88 0 0 22 0 0 0 0 0 1 0 0
14
L 200 50 150 50 -1 0
15
C 200 50 "COM1" 222 50 0 1 22 0 L
16
X "PIN_TEXT" "COM1" 149 38 0 0 22 0 0 2 0 0 1 0 0
17
L 200 100 150 100 -1 0
18
C 200 100 "V+" 222 100 0 1 22 0 L
19
X "PIN_TEXT" "V+" 149 88 0 0 22 0 0 2 0 0 1 0 0
20
L 200 -100 150 -100 -1 0
21
C 200 -100 "V-" 222 -100 0 1 22 0 L
22
X "PIN_TEXT" "V-" 149 -112 0 0 22 0 0 2 0 0 1 0 0
23
L 200 -50 150 -50 -1 0
24
C 200 -50 "COM2" 222 -50 0 1 22 0 L
25
X "PIN_TEXT" "COM2" 149 -62 0 0 22 0 0 2 0 0 1 0 0
26
L -200 50 -150 50 -1 0
27
C -200 50 "VCC2" -222 50 0 1 22 0 R
28
X "PIN_TEXT" "VCC2" -137 38 0 0 22 0 0 0 0 0 1 0 0
29
L -200 -50 -150 -50 -1 0
30
C -200 -50 "GND1" -222 -50 0 1 22 0 R
31
X "PIN_TEXT" "GND1" -137 -62 0 0 22 0 0 0 0 0 1 0 0
32
L -200 -100 -150 -100 -1 0
33
C -200 -100 "GND2" -222 -100 0 1 22 0 R
34
X "PIN_TEXT" "GND2" -137 -112 0 0 22 0 0 0 0 0 1 0 0
35

  
36

  
trunk/librairies/polytech_ge/tel_5/entity/master.tag
1
verilog.v
trunk/librairies/polytech_ge/tel_5/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 29, 2010  11:17:18
trunk/librairies/polytech_ge/tel_5/entity/verilog.v
1
// generated by newgenasym  Wed Sep 29 11:17:18 2010
2

  
3

  
4
module tel_5 (com1, com2, gnd1, gnd2, \v+ , \v- , vcc1, vcc2);
5
    output com1;
6
    output com2;
7
    input gnd1;
8
    input gnd2;
9
    output \v+ ;
10
    output \v- ;
11
    input vcc1;
12
    input vcc2;
13

  
14

  
15
    initial
16
        begin
17
        end
18

  
19
endmodule
trunk/librairies/polytech_ge/tel_5/entity/vhdl.vhd
1
-- generated by newgenasym Wed Sep 29 11:17:18 2010
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity tel_5 is
7
    port (    
8
	COM1:      OUT    STD_LOGIC;    
9
	COM2:      OUT    STD_LOGIC;    
10
	GND1:      IN     STD_LOGIC;    
11
	GND2:      IN     STD_LOGIC;    
12
	\v+\:      OUT    STD_LOGIC;    
13
	\v-\:      OUT    STD_LOGIC;    
14
	VCC1:      IN     STD_LOGIC;    
15
	VCC2:      IN     STD_LOGIC);
16
end tel_5;
trunk/librairies/polytech_ge_beta/mc_7915/metadata/pinlist.txt
16 16
		(CheckOutput 0)
17 17
		(UnknownLoading 0)
18 18
		(PinShape )
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
19 21
	)
20 22

  
21 23
	(Pin
......
35 37
		(CheckOutput 1)
36 38
		(UnknownLoading 0)
37 39
		(PinShape )
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
38 42
	)
39 43

  
40 44
	(Pin
......
54 58
		(CheckOutput 1)
55 59
		(UnknownLoading 0)
56 60
		(PinShape )
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
57 63
	)
58 64

  
59 65

  
trunk/librairies/polytech_ge_beta/mc_7915/metadata/master.tag
1 1
revision.dat
2
revision.log
3
revhistory.log
4
pinlist.txt
trunk/librairies/polytech_ge_beta/mc_7915/metadata/revision.dat
4 4

  
5 5
		(Baselined	0)
6 6

  
7
		(Revision	0.0.4)
7
		(Revision	0.0.7)
8 8

  
9 9
		(ModificationStatus	NULL)
10 10

  
......
24 24

  
25 25
		(LastModifyInfo	
26 26

  
27
			(Time	10/04/07,16:17:53)
27
			(Time	09/29/10,14:25:18)
28 28

  
29
			(User	projets)
29
			(User	spinnete)
30 30

  
31
			(Path	etudiants.mc_7915)
31
			(Path	polytech_ge_beta.mc_7915)
32 32

  
33 33
		)
34 34

  
......
82 82

  
83 83
		(View	Chips
84 84

  
85
			(Checksum	0000000061e284b9)
85
			(Checksum	00000000856e01ff)
86 86

  
87
			(Primitives	1
87
			(Primitives	2
88 88

  
89 89
				(Primitive	MC_7915
90 90

  
......
92 92

  
93 93
						(Baselined	0)
94 94

  
95
						(Revision	0.0.1)
95
						(Revision	0.0.2)
96 96

  
97 97
						(ModificationStatus	NULL)
98 98

  
......
156 156

  
157 157
				)
158 158

  
159
				(Primitive	MC_7915_TO92
160

  
161
					(RevisionInfoBlock	
162

  
163
						(Baselined	0)
164

  
165
						(Revision	0.0.2)
166

  
167
						(ModificationStatus	NULL)
168

  
169
						(Status	Created)
170

  
171
						(ErrorStatus	0)
172

  
173
						(CreateInfo	
174

  
175
							(Time	09/29/10,14:21:18)
176

  
177
							(User	spinnete)
178

  
179
							(Path	polytech_ge_beta.mc_7915)
180

  
181
						)
182

  
183
					)
184

  
185
					(LogicalPhysicalPartRelation	
186

  
187
						(LogicalPart	MC_7915
188

  
189
							(PackType	MC_7915_TO92)
190

  
191
						)
192

  
193
					)
194

  
195
					(Packages	1
196

  
197
						(FunctionGroups	1
198

  
199
							(FunctionGroup	1[1]
200

  
201
								(Linkages	
202

  
203
									(Linkage	Symbol
204

  
205
										(Name	sym_1)
206

  
207
									)
208

  
209
								)
210

  
211
							)
212

  
213
						)
214

  
215
						(Linkages	
216

  
217
							(DefaultFootPrint	
218

  
219
								(Name	to92)
220

  
221
							)
222

  
223
						)
224

  
225
					)
226

  
227
				)
228

  
159 229
			)
160 230

  
161 231
		)
162 232

  
163
		(Checksum	000000001cc103bc)
233
		(Checksum	000000001c9e0380)
164 234

  
165 235
	)
166 236

  
......
168 238

  
169 239
		(ToolName	PDV)
170 240

  
171
		(Version	15.70-p003)
241
		(Version	16.01-s021 (v16-1-53AR))
172 242

  
173
		(License	PCB_librarian_expert)
243
		(License	PCB_design_expert)
174 244

  
175 245
	)
176 246

  
177
	(Checksum	000000001cd403d1)
247
	(Checksum	000000001c55037e)
178 248

  
179 249
)
180 250

  
trunk/librairies/polytech_ge_beta/mc_7915/chips/chips.prt
2 2
primitive 'MC_7915';
3 3
  pin
4 4
    'GND1':
5
      PIN_NUMBER='(2)';
6
      PINUSE='GROUND';
7
      NO_LOAD_CHECK='Both';
8
      NO_IO_CHECK='Both';
9
      NO_ASSERT_CHECK='TRUE';
10
      NO_DIR_CHECK='TRUE';
11
      ALLOW_CONNECT='TRUE';
12
    'IN2':
13
      PIN_NUMBER='(3)';
14
      INPUT_LOAD='(-0.01,0.01)';
15
    'OUT3':
5 16
      PIN_NUMBER='(1)';
17
      OUTPUT_LOAD='(1.0,-1.0)';
18
  end_pin;
19
  body
20
    PART_NAME='MC_7915';
21
    BODY_NAME='MC_7915';
22
    JEDEC_TYPE='TO220_V';
23
    PHYS_DES_PREFIX='U';
24
    CLASS='IC';
25
  end_body;
26
end_primitive;
27

  
28
primitive 'MC_7915_TO92';
29
  pin
30
    'GND1':
31
      PIN_NUMBER='(1)';
6 32
      PINUSE='GROUND';
7 33
      NO_LOAD_CHECK='Both';
8 34
      NO_IO_CHECK='Both';
......
19 45
  body
20 46
    PART_NAME='MC_7915';
21 47
    BODY_NAME='MC_7915';
22
    JEDEC_TYPE='TO220_V';
48
    JEDEC_TYPE='to92';
23 49
    PHYS_DES_PREFIX='U';
24 50
    CLASS='IC';
25 51
  end_body;
trunk/librairies/polytech_ge_beta/mc_7915/entity/master.tag
1
vhdl.vhd
2 1
verilog.v
trunk/librairies/polytech_ge_beta/mc_7915/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Oct  4, 2007  16:24:00
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 29, 2010  14:29:08
trunk/librairies/polytech_ge_beta/mc_7915/entity/verilog.v
1
// generated by newgenasym  Thu Oct 04 16:24:00 2007
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// generated by newgenasym  Wed Sep 29 14:29:08 2010
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module mc_7915 (gnd1, in2, out3);
trunk/librairies/polytech_ge_beta/mc_7915/entity/vhdl.vhd
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-- generated by newgenasym Thu Oct 04 16:24:00 2007
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-- generated by newgenasym Wed Sep 29 14:29:08 2010
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library ieee;
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use     ieee.std_logic_1164.all;

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