Revision 544

View differences:

branch/CHAMBELLON/sp4b1/SP4b1.tws
1
[HIMDBVersion]
2
2.0
3
[DATABASE_VERSION]
4
"1.2" 
5
[CURRENT_PROJECT]
6
"SP4b1" 
7
[GENERAL_DATA]
8
[BREAKPOINTS]
9
[OPEN_WORKSPACE_FILES]
10
[WORKSPACE_FILE_STATES]
11
[LOADED_PROJECTS]
12
"SP4b1" 
13
[END]
branch/CHAMBELLON/sp4b1/sfr32c87.h
1
/************************************************************************************
2
*                                                                                   *
3
*   File name : sfr32c87.h                                                          *
4
*   Contents  : Definition of M32C/87 Group SFR                                     *
5
*                                                                                   *
6
*   Copyright, 2003 RENESAS TECHNOLOGY CORPORATION                                  *
7
*                   AND RENESAS SOLUTIONS CORPORATION                               *
8
*                                                                                   *
9
*   Note      :                                                                     *
10
*                                                                                   *
11
*   Version   : Ver 0.01 (04-09-23) Preliminary                                     *
12
*                       These data made based on M32C/85 Group H/W Manual Rev.0.30  *
13
*   Version   : Ver 0.02 (04-12-02) Preliminary                                     *
14
*   Version   : Ver 0.03 (04-12-22) Preliminary                                     *
15
*   Version   : Ver 0.04 (05-12-08) Preliminary                                     *
16
*   Version   : Ver 0.05 (06-01-23) Preliminary                                     *
17
*                                                                                   *
18
*************************************************************************************/
19
/*
20
  note:
21
    This data is a freeware that SFR for M32C/87 group are described.
22
    RENESAS TECHNOLOGY CORPORATION and RENESAS SOLUTIONS CORPORATION assume
23
    no responsibility for any damage that occurred by this data.
24
*/
25

  
26
/************************************************************************
27
*   declare SFR address                                                 *
28
************************************************************************/
29
#pragma ADDRESS     pm0_addr    0004H       /* Processor mode register 0 */
30
#pragma ADDRESS     pm1_addr    0005H       /* Processor mode register 1 */
31
#pragma ADDRESS     cm0_addr    0006H       /* System clock control register 0 */
32
#pragma ADDRESS     cm1_addr    0007H       /* System clock control register 1 */
33

  
34
#pragma ADDRESS     aier_addr   0009H       /* Address match interrupt enable register */
35
#pragma ADDRESS     prcr_addr   000aH       /* Protect register */
36
#pragma ADDRESS     ds_addr     000bH       /* External data bus width control register */
37
#pragma ADDRESS     mcd_addr    000cH       /* Main clock division register */
38
#pragma ADDRESS     cm2_addr    000dH       /* Oscillation stop detect register */
39
#pragma ADDRESS     wdts_addr   000eH       /* Watchdog timer start register */
40
#pragma ADDRESS     wdc_addr    000fH       /* Watchdog timer control register */
41
#pragma ADDRESS     rmad0_addr  0010H       /* Address match interrupt register 0 */
42
#pragma ADDRESS     pm2_addr    0013H       /* Processor mode register 2 */
43
#pragma ADDRESS     rmad1_addr  0014H       /* Address match interrupt register 1 */
44
#pragma ADDRESS     vcr2_addr   0017H       /* Voltage detection register 2 */
45
#pragma ADDRESS     rmad2_addr  0018H       /* Address match interrupt register 2 */
46
#pragma ADDRESS     vcr1_addr   001bH       /* Voltage detection register 1 */
47
#pragma ADDRESS     rmad3_addr  001cH       /* Address match interrupt register 3 */
48

  
49

  
50
#pragma ADDRESS     plc_addr    0026H       /* PLL control register */
51
#pragma ADDRESS     plc0_addr   0026H       /* PLL control register 0 */
52
#pragma ADDRESS     plc1_addr   0027H       /* PLL control register 1 */
53
#pragma ADDRESS     rmad4_addr  0028H       /* Address match interrupt register 4 */
54

  
55
#pragma ADDRESS     rmad5_addr  002CH       /* Address match interrupt register 5 */
56
#pragma ADDRESS     d4int_addr  002FH       /* Voltage down detect interrupt register */
57

  
58

  
59
#pragma ADDRESS     rmad6_addr  0038H       /* Address match interrupt register 6 */
60
#pragma ADDRESS     rmad7_addr  003CH       /* Address match interrupt register 7 */
61

  
62

  
63
#pragma ADDRESS     ewcr0_addr  0048H       /* External space wait control register 0 */
64
#pragma ADDRESS     ewcr1_addr  0049H       /* External space wait control register 1 */
65
#pragma ADDRESS     ewcr2_addr  004AH       /* External space wait control register 2 */
66
#pragma ADDRESS     ewcr3_addr  004BH       /* External space wait control register 3 */
67

  
68

  
69
#pragma ADDRESS     fmr1_addr   0055H       /* Flash Memory Control Register 1 */
70

  
71
#pragma ADDRESS     fmr_addr    0057H       /* Flash memory control register 0 */
72
#pragma ADDRESS     fmr0_addr   0057H       /* Flash memory control register 0 */
73

  
74

  
75
#pragma ADDRESS     dm0ic_addr  0068H       /* DMA0 interrupt control register */
76
#pragma ADDRESS     tb5ic_addr  0069H       /* Timer B5 interrupt register */
77
#pragma ADDRESS     dm2ic_addr  006aH       /* DMA2 interrupt register */
78
#pragma ADDRESS     s2ric_addr  006bH       /* UART2 receive/ack interrupt control register */
79
#pragma ADDRESS     ta0ic_addr  006cH       /* Timer A0 interrupt control register */
80
#pragma ADDRESS     s3ric_addr  006dH       /* UART3 receive/ack interrupt control register */
81
#pragma ADDRESS     ta2ic_addr  006eH       /* Timer A2 interrupt control register */
82
#pragma ADDRESS     s4ric_addr  006fH       /* UART4 receive/ack interrupt control register */
83
#pragma ADDRESS     ta4ic_addr  0070H       /* Timer A4 interrupt control register */
84
#pragma ADDRESS     bcn0ic_addr 0071H       /* Bus collision (UART0) interrupt control register */
85
#pragma ADDRESS     bcn3ic_addr 0071H       /* Bus collision (UART3) interrupt control register */
86
#pragma ADDRESS     s0ric_addr  0072H       /* UART0 receive interrupt control register */
87
#pragma ADDRESS     ad0ic_addr  0073H       /* A/D0 conversion interrupt control register */
88
#pragma ADDRESS     s1ric_addr  0074H       /* UART1 receive interrupt control register */
89
#pragma ADDRESS     iio0ic_addr 0075H       /* Intelligent I/O interrupt control register 0 */
90
#pragma ADDRESS     can3ic_addr 0075H       /* CAN interrupt 3 control register */
91
#pragma ADDRESS     tb1ic_addr  0076H       /* Timer B1 interrupt control register */
92
#pragma ADDRESS     iio2ic_addr 0077H       /* Intelligent I/O interrupt control register 2 */
93
#pragma ADDRESS     tb3ic_addr  0078H       /* Timer B3 interrupt control register */
94
#pragma ADDRESS     iio4ic_addr 0079H       /* Intelligent I/O interrupt control register 4 */
95
#pragma ADDRESS     int5ic_addr 007aH       /* INT5~ interrupt control register */
96
#pragma ADDRESS     iio6ic_addr 007bH       /* Intelligent I/O interrupt control register 6 */
97
#pragma ADDRESS     int3ic_addr 007cH       /* INT3~ interrupt control register */
98
#pragma ADDRESS     iio8ic_addr 007dH       /* Intelligent I/O interrupt control register 8 */
99
#pragma ADDRESS     int1ic_addr 007eH       /* INT1~ interrupt control register */
100
#pragma ADDRESS     iio10ic_addr 007fH      /* Intelligent I/O interrupt control register 10 */
101
#pragma ADDRESS     can1ic_addr 007fH       /* CAN Interrupt 1 Control Register */
102

  
103
#pragma ADDRESS     iio11ic_addr 0081H      /* Intelligent I/O interrupt control register 11 */
104
#pragma ADDRESS     can2ic_addr 0081H       /* CAN Interrupt 2 Control Register */
105

  
106

  
107
#pragma ADDRESS     dm1ic_addr  0088H       /* DMA1 interrupt control register */
108
#pragma ADDRESS     s2tic_addr  0089H       /* UART2 transmit/nack interrupt control register */
109
#pragma ADDRESS     dm3ic_addr  008aH       /* DMA3 interrupt control register */
110
#pragma ADDRESS     s3tic_addr  008bH       /* UART3 transmit/nack interrupt control register */
111
#pragma ADDRESS     ta1ic_addr  008cH       /* Timer A1 interrupt control register */
112
#pragma ADDRESS     s4tic_addr  008dH       /* UART4 transmit/nack interrupt control register */
113
#pragma ADDRESS     ta3ic_addr  008eH       /* Timer A3 interrupt control register */
114
#pragma ADDRESS     bcn2ic_addr 008fH       /* Bus collision (UART2) interrupt control register */
115
#pragma ADDRESS     s0tic_addr  0090H       /* UART0 transmit interrupt control register */
116
#pragma ADDRESS     bcn1ic_addr 0091H       /* Bus collision (UART1) interrupt control register*/
117
#pragma ADDRESS     bcn4ic_addr 0091H       /* Bus collision (UART4) interrupt control register */
118
#pragma ADDRESS     s1tic_addr  0092H       /* UART1 transmit interrupt control register */
119
#pragma ADDRESS     kupic_addr  0093H       /* Key input interrupt control register */
120
#pragma ADDRESS     tb0ic_addr  0094H       /* Timer B0 interrupt control register */
121
#pragma ADDRESS     iio1ic_addr 0095H       /* Intelligent I/O interrupt control register 1 */
122
#pragma ADDRESS     can4ic_addr 0095H       /* CAN Interrupt 4 Control Register */
123
#pragma ADDRESS     tb2ic_addr  0096H       /* Timer B2 interrupt control register */
124
#pragma ADDRESS     iio3ic_addr 0097H       /* Intelligent I/O interrupt control register 3 */
125
#pragma ADDRESS     tb4ic_addr  0098H       /* Timer B4 interrupt control register */
126
#pragma ADDRESS     iio5ic_addr 0099H       /* Intelligent I/O interrupt control register 5 */
127
#pragma ADDRESS     can5ic_addr 0099H       /* CAN Interrupt 5 Control Register */
128
#pragma ADDRESS     int4ic_addr 009aH       /* INT4~ interrupt control register */
129
#pragma ADDRESS     iio7ic_addr 009bH       /* Intelligent I/O interrupt control register 7 */
130
#pragma ADDRESS     int2ic_addr 009cH       /* INT2~ interrupt control register */
131
#pragma ADDRESS     iio9ic_addr 009dH       /* Intelligent I/O interrupt control register 9 */
132
#pragma ADDRESS     can0ic_addr 009dH       /* CAN0 Interrupt Control Register*/
133
#pragma ADDRESS     int0ic_addr 009eH       /* INT0~ interrupt control register */
134
#pragma ADDRESS     rlvl_addr   009fH       /* Exit priority register */
135
#pragma ADDRESS     iio0ir_addr 00a0H       /* Interrupt request register 0 */
136
#pragma ADDRESS     iio1ir_addr 00a1H       /* Interrupt request register 1 */
137
#pragma ADDRESS     iio2ir_addr 00a2H       /* Interrupt request register 2 */
138
#pragma ADDRESS     iio3ir_addr 00a3H       /* Interrupt request register 3 */
139
#pragma ADDRESS     iio4ir_addr 00a4H       /* Interrupt request register 4 */
140
#pragma ADDRESS     iio5ir_addr 00a5H       /* Interrupt request register 5 */
141
#pragma ADDRESS     iio6ir_addr 00a6H       /* Interrupt request register 6 */
142
#pragma ADDRESS     iio7ir_addr 00a7H       /* Interrupt request register 7 */
143
#pragma ADDRESS     iio8ir_addr 00a8H       /* Interrupt request register 8 */
144
#pragma ADDRESS     iio9ir_addr 00a9H       /* Interrupt request register 9 */
145
#pragma ADDRESS     iio10ir_addr 00aaH      /* Interrupt request register 10 */
146
#pragma ADDRESS     iio11ir_addr 00abH      /* Interrupt request register 11 */
147

  
148

  
149
#pragma ADDRESS     iio0ie_addr 00b0H       /* Interrupt enable register 0 */
150
#pragma ADDRESS     iio1ie_addr 00b1H       /* Interrupt enable register 1 */
151
#pragma ADDRESS     iio2ie_addr 00b2H       /* Interrupt enable register 2 */
152
#pragma ADDRESS     iio3ie_addr 00b3H       /* Interrupt enable register 3 */
153
#pragma ADDRESS     iio4ie_addr 00b4H       /* Interrupt enable register 4 */
154
#pragma ADDRESS     iio5ie_addr 00b5H       /* Interrupt enable register 5 */
155
#pragma ADDRESS     iio6ie_addr 00b6H       /* Interrupt enable register 6 */
156
#pragma ADDRESS     iio7ie_addr 00b7H       /* Interrupt enable register 7 */
157
#pragma ADDRESS     iio8ie_addr 00b8H       /* Interrupt enable register 8 */
158
#pragma ADDRESS     iio9ie_addr 00b9H       /* Interrupt enable register 9 */
159
#pragma ADDRESS     iio10ie_addr 00baH      /* Interrupt enable register 10 */
160
#pragma ADDRESS     iio11ie_addr 00bbH      /* Interrupt enable register 11 */
161

  
162

  
163
#pragma ADDRESS     g0rb_addr   00e8H       /* SI/O receive buffer register 0 */
164
#pragma ADDRESS     g0tb_addr   00eaH       /* Transmit buffer register 0 */
165
#pragma ADDRESS     g0dr_addr   00eaH       /* Receive data register 0 */
166

  
167
#pragma ADDRESS     g0ri_addr   00ecH       /* Receive input register 0 */
168
#pragma ADDRESS     g0mr_addr   00edH       /* SI/O communication control register 0 */
169
#pragma ADDRESS     g0to_addr   00eeH       /* Transmit output register 0 */
170
#pragma ADDRESS     g0cr_addr   00efH       /* SI/O communication control register 0 */
171
#pragma ADDRESS     g0cmp0_addr 00f0H       /* Data compare register 00 */
172
#pragma ADDRESS     g0cmp1_addr 00f1H       /* Data compare register 01 */
173
#pragma ADDRESS     g0cmp2_addr 00f2H       /* Data compare register 02 */
174
#pragma ADDRESS     g0cmp3_addr 00f3H       /* Data compare register 03 */
175
#pragma ADDRESS     g0msk0_addr 00f4H       /* Data mask register 00 */
176
#pragma ADDRESS     g0msk1_addr 00f5H       /* Data mask register 01 */
177
#pragma ADDRESS     ccs_addr    00f6H       /* Communication clock select register */
178

  
179
#pragma ADDRESS     g0rcrc_addr 00f8H       /* Receive CRC code register 0 */
180
#pragma ADDRESS     g0tcrc_addr 00faH       /* Transmit CRC code register 0 */
181
#pragma ADDRESS     g0emr_addr  00fcH       /* SI/O expansion mode register 0 */
182
#pragma ADDRESS     g0erc_addr  00fdH       /* SI/O expansion receive control register 0 */
183
#pragma ADDRESS     g0irf_addr  00feH       /* SI/O special communication interrupt detect register 0 */
184
#pragma ADDRESS     g0etc_addr  00ffH       /* SI/O expansion transmit control register 0 */
185
#pragma ADDRESS     g1tm0_addr  0100H       /* Time measurement register 10 */
186
#pragma ADDRESS     g1po0_addr  0100H       /* Waveform generate register 10 */
187
#pragma ADDRESS     g1tm1_addr  0102H       /* Time measurement register 11 */
188
#pragma ADDRESS     g1po1_addr  0102H       /* Waveform generate register 11 */
189
#pragma ADDRESS     g1tm2_addr  0104H       /* Time measurement register 12 */
190
#pragma ADDRESS     g1po2_addr  0104H       /* Waveform generate register 12 */
191
#pragma ADDRESS     g1tm3_addr  0106H       /* Time measurement register 13 */
192
#pragma ADDRESS     g1po3_addr  0106H       /* Waveform generate register 13 */
193
#pragma ADDRESS     g1tm4_addr  0108H       /* Time measurement register 14 */
194
#pragma ADDRESS     g1po4_addr  0108H       /* Waveform generate register 14 */
195
#pragma ADDRESS     g1tm5_addr  010aH       /* Time measurement register 15 */
196
#pragma ADDRESS     g1po5_addr  010aH       /* Waveform generate register 15 */
197
#pragma ADDRESS     g1tm6_addr  010cH       /* Time measurement register 16 */
198
#pragma ADDRESS     g1po6_addr  010cH       /* Waveform generate register 16 */
199
#pragma ADDRESS     g1tm7_addr  010eH       /* Time measurement register 17 */
200
#pragma ADDRESS     g1po7_addr  010eH       /* Waveform generate register 17 */
201
#pragma ADDRESS     g1pocr0_addr 0110H      /* Waveform generate control register 10 */
202
#pragma ADDRESS     g1pocr1_addr 0111H      /* Waveform generate control register 11 */
203
#pragma ADDRESS     g1pocr2_addr 0112H      /* Waveform generate control register 12 */
204
#pragma ADDRESS     g1pocr3_addr 0113H      /* Waveform generate control register 13 */
205
#pragma ADDRESS     g1pocr4_addr 0114H      /* Waveform generate control register 14 */
206
#pragma ADDRESS     g1pocr5_addr 0115H      /* Waveform generate control register 15 */
207
#pragma ADDRESS     g1pocr6_addr 0116H      /* Waveform generate control register 16 */
208
#pragma ADDRESS     g1pocr7_addr 0117H      /* Waveform generate control register 17 */
209
#pragma ADDRESS     g1tmcr0_addr 0118H      /* Time measurement control register 10 */
210
#pragma ADDRESS     g1tmcr1_addr 0119H      /* Time measurement control register 11 */
211
#pragma ADDRESS     g1tmcr2_addr 011aH      /* Time measurement control register 12 */
212
#pragma ADDRESS     g1tmcr3_addr 011bH      /* Time measurement control register 13 */
213
#pragma ADDRESS     g1tmcr4_addr 011cH      /* Time measurement control register 14 */
214
#pragma ADDRESS     g1tmcr5_addr 011dH      /* Time measurement control register 15 */
215
#pragma ADDRESS     g1tmcr6_addr 011eH      /* Time measurement control register 16 */
216
#pragma ADDRESS     g1tmcr7_addr 011fH      /* Time measurement control register 17 */
217
#pragma ADDRESS     g1bt_addr    0120H      /* Base timer register 1 */
218
#pragma ADDRESS     g1bcr0_addr  0122H      /* Base timer control register 10 */
219
#pragma ADDRESS     g1bcr1_addr  0123H      /* Base timer control register 11 */
220
#pragma ADDRESS     g1tpr6_addr  0124H      /* Time measurement prescaler register 16 */
221
#pragma ADDRESS     g1tpr7_addr  0125H      /* Time measurement prescaler register 17 */
222
#pragma ADDRESS     g1fe_addr    0126H      /* Function enable register 1 */
223
#pragma ADDRESS     g1fs_addr    0127H      /* Function select register 1 */
224
#pragma ADDRESS     g1rb_addr    0128H      /* SI/O receive buffer register 1 */
225
#pragma ADDRESS     g1tb_addr    012aH      /* Transmit buffer register 1 */
226
#pragma ADDRESS     g1dr_addr    012aH      /* Receive data register 1 */
227

  
228
#pragma ADDRESS     g1ri_addr    012cH      /* Receive input register 1 */
229
#pragma ADDRESS     g1mr_addr    012dH      /* SI/O communication mode register 1 */
230
#pragma ADDRESS     g1to_addr    012eH      /* Transmit output register 1 */
231
#pragma ADDRESS     g1cr_addr    012fH      /* SI/O communication control register 1 */
232
#pragma ADDRESS     g1cmp0_addr  0130H      /* Data compare register 10 */
233
#pragma ADDRESS     g1cmp1_addr  0131H      /* Data compare register 11 */
234
#pragma ADDRESS     g1cmp2_addr  0132H      /* Data compare register 12 */
235
#pragma ADDRESS     g1cmp3_addr  0133H      /* Data compare register 13 */
236
#pragma ADDRESS     g1msk0_addr  0134H      /* Data mask register 10 */
237
#pragma ADDRESS     g1msk1_addr  0135H      /* Data mask register 11 */
238

  
239

  
240
#pragma ADDRESS     g1rcrc_addr  0138H      /* Receive CRC code register 1 */
241
#pragma ADDRESS     g1tcrc_addr  013aH      /* Transmit CRC code register 1 */
242
#pragma ADDRESS     g1emr_addr   013cH      /* SI/O extended mode register 1 */
243
#pragma ADDRESS     g1erc_addr   013dH      /* SI/O extended receive control register 1 */
244
#pragma ADDRESS     g1irf_addr   013eH      /* SI/O special communication interrupt detect register 1 */
245
#pragma ADDRESS     g1etc_addr   013fH      /* SI/O extended transmit control register 1 */
246

  
247
#pragma ADDRESS     g2po0_addr   0140H
248
#pragma ADDRESS     g2po1_addr   0142H
249
#pragma ADDRESS     g2po2_addr   0144H
250
#pragma ADDRESS     g2po3_addr   0146H
251
#pragma ADDRESS     g2po4_addr   0148H
252
#pragma ADDRESS     g2po5_addr   014aH
253
#pragma ADDRESS     g2po6_addr   014cH
254
#pragma ADDRESS     g2po7_addr   014eH
255
#pragma ADDRESS     g2pocr0_addr 0150H
256
#pragma ADDRESS     g2pocr1_addr 0151H
257
#pragma ADDRESS     g2pocr2_addr 0152H
258
#pragma ADDRESS     g2pocr3_addr 0153H
259
#pragma ADDRESS     g2pocr4_addr 0154H
260
#pragma ADDRESS     g2pocr5_addr 0155H
261
#pragma ADDRESS     g2pocr6_addr 0156H
262
#pragma ADDRESS     g2pocr7_addr 0157H
263

  
264

  
265
#pragma ADDRESS     g2bt_addr    0160H
266
#pragma ADDRESS     g2bcr0_addr  0162H
267
#pragma ADDRESS     g2bcr1_addr  0163H
268
#pragma ADDRESS     btsr_addr    0164H
269

  
270
#pragma ADDRESS     g2fe_addr    0166H
271
#pragma ADDRESS     g2rtp_addr   0167H
272

  
273

  
274
#pragma ADDRESS     g2mr_addr    016aH
275
#pragma ADDRESS     g2cr_addr    016bH
276
#pragma ADDRESS     g2tb_addr    016cH
277
#pragma ADDRESS     g2rb_addr    016eH
278
#pragma ADDRESS     iear_addr    0170H
279
#pragma ADDRESS     iecr_addr    0172H
280
#pragma ADDRESS     ietif_addr   0173H
281
#pragma ADDRESS     ierif_addr   0174H
282

  
283

  
284
#pragma ADDRESS     ipsb_addr    0177H      /* Input function select register B */
285
#pragma ADDRESS     ips_addr     0178H      /* Input function select register */
286
#pragma ADDRESS     ipsa_addr    0179H      /* Input function select register A */
287

  
288

  
289
#pragma ADDRESS     u5mr_addr   01c0H       /* UART5 transmit/receive mode register */
290
#pragma ADDRESS     u5brg_addr  01c1H       /* UART5 bit rate generator */
291
#pragma ADDRESS     u5tb_addr   01c2H       /* UART5 transmit buffer register */
292
#pragma ADDRESS     u5c0_addr   01c4H       /* UART5 transmit/receive control register 0 */
293
#pragma ADDRESS     u5c1_addr   01c5H       /* UART5 transmit/receive control register 1 */
294
#pragma ADDRESS     u5rb_addr   01c6H       /* UART5 receive buffer register */
295
#pragma ADDRESS     u6mr_addr   01c8H       /* UART6 transmit/receive mode register */
296
#pragma ADDRESS     u6brg_addr  01c9H       /* UART6 bit rate generator */
297
#pragma ADDRESS     u6tb_addr   01caH       /* UART6 transmit buffer register */
298
#pragma ADDRESS     u6c0_addr   01ccH       /* UART6 transmit/receive control register 0 */
299
#pragma ADDRESS     u6c1_addr   01cdH       /* UART6 transmit/receive control register 1 */
300
#pragma ADDRESS     u6rb_addr   01ceH       /* UART6 receive buffer register */
301
#pragma ADDRESS     u56con_addr 01d0H
302
#pragma ADDRESS     u56is_addr  01d1H
303

  
304

  
305
#pragma ADDRESS     rtp0r_addr  01d8H
306
#pragma ADDRESS     rtp1r_addr  01d9H
307
#pragma ADDRESS     rtp2r_addr  01daH
308
#pragma ADDRESS     rtp3r_addr  01dbH
309

  
310

  
311

  
312
/************************************************************************
313
*   CAN 0 SFR Address area                                              *
314
************************************************************************/
315
#pragma ADDRESS     c0slot          01e0H      /* CAN0 Message Slot Buffer */
316
#pragma ADDRESS     c0slot0         01e0H      /* CAN0 Message Slot Buffer 0 */
317
#pragma ADDRESS     c0slot1         01f0H      /* CAN0 Message Slot Buffer 1 */
318
#pragma ADDRESS     c0ctlr0_addr    0200H      /* CAN0 Control Register 0 */
319
#pragma ADDRESS     c0str_addr      0202H      /* CAN0 Status Register */
320
#pragma ADDRESS     c0idr_addr      0204H      /* CAN0 Extended ID Register */
321
#pragma ADDRESS     c0conr_addr     0206H      /* CAN0 Configuration Register */
322
#pragma ADDRESS     c0tsr_addr      0208H      /* CAN0 Time Stamp Register */
323
#pragma ADDRESS     c0tec_addr      020aH      /* CAN0 Transmit Error Counter */
324
#pragma ADDRESS     c0rec_addr      020bH      /* CAN0 Receive Error Counter */
325
#pragma ADDRESS     c0sistr_addr    020cH      /* CAN0 Slot Interrupt Status Register */
326
#pragma ADDRESS     c0simkr_addr    0210H      /* CAN0 Slot Interrupt Mask Register */
327
#pragma ADDRESS     c0eimkr_addr    0214H      /* CAN0 Error Interrupt Mask Register */
328
#pragma ADDRESS     c0eistr_addr    0215H      /* CAN0 Error Interrupt Status Register */
329
#pragma ADDRESS     c0efr_addr      0216H      /* CAN0 Error Factor Register  */
330
#pragma ADDRESS     c0brp_addr      0217H      /* CAN0 Baud Rate Prescaler */
331
#pragma ADDRESS     c0mdr_addr      0219H      /* CAN0 Mode Register */
332
#pragma ADDRESS     c0ssctlr_addr   0220H      /* (BANK0) CAN0 Single Shot Control Register */
333
#pragma ADDRESS     c0ssstr_addr    0224H      /* (BANK0) CAN0 Single Shot Status Register */
334
#pragma ADDRESS     c0mctl          0230H      /* (BANK0) CAN0 Message Control Register */
335
#pragma ADDRESS     c0mctl0         0230H      /* (BANK0) CAN0 Message Slot0 Control Register */
336
#pragma ADDRESS     c0mctl1         0231H      /* (BANK0) CAN0 Message Slot1 Control Register */
337
#pragma ADDRESS     c0mctl2         0232H      /* (BANK0) CAN0 Message Slot2 Control Register */
338
#pragma ADDRESS     c0mctl3         0233H      /* (BANK0) CAN0 Message Slot3 Control Register */
339
#pragma ADDRESS     c0mctl4         0234H      /* (BANK0) CAN0 Message Slot4 Control Register */
340
#pragma ADDRESS     c0mctl5         0235H      /* (BANK0) CAN0 Message Slot5 Control Register */
341
#pragma ADDRESS     c0mctl6         0236H      /* (BANK0) CAN0 Message Slot6 Control Register */
342
#pragma ADDRESS     c0mctl7         0237H      /* (BANK0) CAN0 Message Slot7 Control Register */
343
#pragma ADDRESS     c0mctl8         0238H      /* (BANK0) CAN0 Message Slot8 Control Register */
344
#pragma ADDRESS     c0mctl9         0239H      /* (BANK0) CAN0 Message Slot9 Control Register */
345
#pragma ADDRESS     c0mctl10        023aH      /* (BANK0) CAN0 Message Slot10 Control Register */
346
#pragma ADDRESS     c0mctl11        023bH      /* (BANK0) CAN0 Message Slot11 Control Register */
347
#pragma ADDRESS     c0mctl12        023cH      /* (BANK0) CAN0 Message Slot12 Control Register */
348
#pragma ADDRESS     c0mctl13        023dH      /* (BANK0) CAN0 Message Slot13 Control Register */
349
#pragma ADDRESS     c0mctl14        023eH      /* (BANK0) CAN0 Message Slot14 Control Register */
350
#pragma ADDRESS     c0mctl15        023fH      /* (BANK0) CAN0 Message Slot15 Control Register */
351
#pragma ADDRESS     c0gmr           0228H      /* (BANK1) CAN0 Global Mask Register */
352
#pragma ADDRESS     c0gmr0_addr     0228H      /* (BANK1) CAN0 Global Mask Register 0 */
353
#pragma ADDRESS     c0gmr1_addr     0229H      /* (BANK1) CAN0 Global Mask Register 1 */
354
#pragma ADDRESS     c0gmr2_addr     022aH      /* (BANK1) CAN0 Global Mask Register 2 */
355
#pragma ADDRESS     c0gmr3_addr     022bH      /* (BANK1) CAN0 Global Mask Register 3 */
356
#pragma ADDRESS     c0gmr4_addr     022cH      /* (BANK1) CAN0 Global Mask Register 4 */
357
#pragma ADDRESS     c0lmar          0230H      /* (BANK1) CAN0 Local Mask A Register */
358
#pragma ADDRESS     c0lmar0_addr    0230H      /* (BANK1) CAN0 Local Mask A Register 0 */
359
#pragma ADDRESS     c0lmar1_addr    0231H      /* (BANK1) CAN0 Local Mask A Register 1 */
360
#pragma ADDRESS     c0lmar2_addr    0232H      /* (BANK1) CAN0 Local Mask A Register 2 */
361
#pragma ADDRESS     c0lmar3_addr    0233H      /* (BANK1) CAN0 Local Mask A Register 3 */
362
#pragma ADDRESS     c0lmar4_addr    0234H      /* (BANK1) CAN0 Local Mask A Register 4 */
363
#pragma ADDRESS     c0lmbr          0238H      /* (BANK1) CAN0 Local Mask B Register */
364
#pragma ADDRESS     c0lmbr0_addr    0238H      /* (BANK1) CAN0 Local Mask B Register 0 */
365
#pragma ADDRESS     c0lmbr1_addr    0239H      /* (BANK1) CAN0 Local Mask B Register 1 */
366
#pragma ADDRESS     c0lmbr2_addr    023aH      /* (BANK1) CAN0 Local Mask B Register 2 */
367
#pragma ADDRESS     c0lmbr3_addr    023bH      /* (BANK1) CAN0 Local Mask B Register 3 */
368
#pragma ADDRESS     c0lmbr4_addr    023cH      /* (BANK1) CAN0 Local Mask B Register 4 */
369
#pragma ADDRESS     c0sbs_addr      0240H      /* CAN0 Slot Buffer Select Register */
370
#pragma ADDRESS     c0ctlr1_addr    0241H      /* CAN0 Control Register 1 */
371
#pragma ADDRESS     c0slpr_addr     0242H      /* CAN0 Sleep Control Register */
372
#pragma ADDRESS     c0afs_addr      0244H      /* CAN0 Acceptance Filter Support Register */
373

  
374

  
375
/************************************************************************
376
*   CAN 1 SFR Address area                                              *
377
************************************************************************/
378
#pragma ADDRESS     c1slot          0260H      /* CAN1 Message Slot Buffer */
379
#pragma ADDRESS     c1slot0         0260H      /* CAN1 Message Slot Buffer 0 */
380
#pragma ADDRESS     c1slot1         0270H      /* CAN1 Message Slot Buffer 1 */
381
#pragma ADDRESS     c1ctlr0_addr    0280H      /* CAN1 Control Register 0 */
382
#pragma ADDRESS     c1str_addr      0282H      /* CAN1 Status Register */
383
#pragma ADDRESS     c1idr_addr      0284H      /* CAN1 Extended ID Register */
384
#pragma ADDRESS     c1conr_addr     0286H      /* CAN1 Configuration Register */
385
#pragma ADDRESS     c1tsr_addr      0288H      /* CAN1 Time Stamp Register */
386
#pragma ADDRESS     c1tec_addr      028aH      /* CAN1 Transmit Error Counter */
387
#pragma ADDRESS     c1rec_addr      028bH      /* CAN1 Receive Error Counter */
388
#pragma ADDRESS     c1sistr_addr    028cH      /* CAN1 Slot Interrupt Status Register */
389
#pragma ADDRESS     c1simkr_addr    0290H      /* CAN1 Slot Interrupt Mask Register */
390
#pragma ADDRESS     c1eimkr_addr    0294H      /* CAN1 Error Interrupt Mask Register */
391
#pragma ADDRESS     c1eistr_addr    0295H      /* CAN1 Error Interrupt Status Register */
392
#pragma ADDRESS     c1efr_addr      0296H      /* CAN1 Error Factor Register  */
393
#pragma ADDRESS     c1brp_addr      0297H      /* CAN1 Baud Rate Prescaler */
394
#pragma ADDRESS     c1mdr_addr      0299H      /* CAN1 Mode Register */
395
#pragma ADDRESS     c1ssctlr_addr   02A0H      /* (BANK0) CAN1 Single Shot Control Register */
396
#pragma ADDRESS     c1ssstr_addr    02A4H      /* (BANK0) CAN1 Single Shot Status Register */
397
#pragma ADDRESS     c1mctl          02B0H      /* (BANK0) CAN1 Message Control Register */
398
#pragma ADDRESS     c1mctl0         02B0H      /* (BANK0) CAN1 Message Slot0 Control Register */
399
#pragma ADDRESS     c1mctl1         02B1H      /* (BANK0) CAN1 Message Slot1 Control Register */
400
#pragma ADDRESS     c1mctl2         02B2H      /* (BANK0) CAN1 Message Slot2 Control Register */
401
#pragma ADDRESS     c1mctl3         02B3H      /* (BANK0) CAN1 Message Slot3 Control Register */
402
#pragma ADDRESS     c1mctl4         02B4H      /* (BANK0) CAN1 Message Slot4 Control Register */
403
#pragma ADDRESS     c1mctl5         02B5H      /* (BANK0) CAN1 Message Slot5 Control Register */
404
#pragma ADDRESS     c1mctl6         02B6H      /* (BANK0) CAN1 Message Slot6 Control Register */
405
#pragma ADDRESS     c1mctl7         02B7H      /* (BANK0) CAN1 Message Slot7 Control Register */
406
#pragma ADDRESS     c1mctl8         02B8H      /* (BANK0) CAN1 Message Slot8 Control Register */
407
#pragma ADDRESS     c1mctl9         02B9H      /* (BANK0) CAN1 Message Slot9 Control Register */
408
#pragma ADDRESS     c1mctl10        02baH      /* (BANK0) CAN1 Message Slot10 Control Register */
409
#pragma ADDRESS     c1mctl11        02bbH      /* (BANK0) CAN1 Message Slot11 Control Register */
410
#pragma ADDRESS     c1mctl12        02bcH      /* (BANK0) CAN1 Message Slot12 Control Register */
411
#pragma ADDRESS     c1mctl13        02bdH      /* (BANK0) CAN1 Message Slot13 Control Register */
412
#pragma ADDRESS     c1mctl14        02beH      /* (BANK0) CAN1 Message Slot14 Control Register */
413
#pragma ADDRESS     c1mctl15        02bfH      /* (BANK0) CAN1 Message Slot15 Control Register */
414
#pragma ADDRESS     c1gmr           02a8H      /* (BANK1) CAN1 Global Mask Register */
415
#pragma ADDRESS     c1gmr0_addr     02a8H      /* (BANK1) CAN1 Global Mask Register 0 */
416
#pragma ADDRESS     c1gmr1_addr     02a9H      /* (BANK1) CAN1 Global Mask Register 1 */
417
#pragma ADDRESS     c1gmr2_addr     02aaH      /* (BANK1) CAN1 Global Mask Register 2 */
418
#pragma ADDRESS     c1gmr3_addr     02abH      /* (BANK1) CAN1 Global Mask Register 3 */
419
#pragma ADDRESS     c1gmr4_addr     02acH      /* (BANK1) CAN1 Global Mask Register 4 */
420
#pragma ADDRESS     c1lmar          02b0H      /* (BANK1) CAN1 Local Mask A Register */
421
#pragma ADDRESS     c1lmar0_addr    02b0H      /* (BANK1) CAN1 Local Mask A Register 0 */
422
#pragma ADDRESS     c1lmar1_addr    02b1H      /* (BANK1) CAN1 Local Mask A Register 1 */
423
#pragma ADDRESS     c1lmar2_addr    02b2H      /* (BANK1) CAN1 Local Mask A Register 2 */
424
#pragma ADDRESS     c1lmar3_addr    02b3H      /* (BANK1) CAN1 Local Mask A Register 3 */
425
#pragma ADDRESS     c1lmar4_addr    02b4H      /* (BANK1) CAN1 Local Mask A Register 4 */
426
#pragma ADDRESS     c1lmbr          02b8H      /* (BANK1) CAN1 Local Mask B Register */
427
#pragma ADDRESS     c1lmbr0_addr    02b8H      /* (BANK1) CAN1 Local Mask B Register 0 */
428
#pragma ADDRESS     c1lmbr1_addr    02b9H      /* (BANK1) CAN1 Local Mask B Register 1 */
429
#pragma ADDRESS     c1lmbr2_addr    02baH      /* (BANK1) CAN1 Local Mask B Register 2 */
430
#pragma ADDRESS     c1lmbr3_addr    02bbH      /* (BANK1) CAN1 Local Mask B Register 3 */
431
#pragma ADDRESS     c1lmbr4_addr    02bcH      /* (BANK1) CAN1 Local Mask B Register 4 */
432
#pragma ADDRESS     c1sbs_addr      0250H      /* CAN1 Slot Buffer Select Register */
433
#pragma ADDRESS     c1ctlr1_addr    0251H      /* CAN1 Control Register 1 */
434
#pragma ADDRESS     c1slpr_addr     0252H      /* CAN1 Sleep Control Register */
435
#pragma ADDRESS     c1afs_addr      0254H      /* CAN1 Acceptance Filter Support Register */
436

  
437
/************************************************************************
438
*                                                                       *
439
************************************************************************/
440
#pragma ADDRESS     x0r_addr    02c0H       /* X0 register */
441
#pragma ADDRESS     y0r_addr    02c0H       /* Y0 register */
442
#pragma ADDRESS     x1r_addr    02c2H       /* X1 register */
443
#pragma ADDRESS     y1r_addr    02c2H       /* Y1 register */
444
#pragma ADDRESS     x2r_addr    02c4H       /* X2 register */
445
#pragma ADDRESS     y2r_addr    02c4H       /* Y2 register */
446
#pragma ADDRESS     x3r_addr    02c6H       /* X3 register */
447
#pragma ADDRESS     y3r_addr    02c6H       /* Y3 register */
448
#pragma ADDRESS     x4r_addr    02c8H       /* X4 register */
449
#pragma ADDRESS     y4r_addr    02c8H       /* Y4 register */
450
#pragma ADDRESS     x5r_addr    02caH       /* X5 register */
451
#pragma ADDRESS     y5r_addr    02caH       /* Y5 register */
452
#pragma ADDRESS     x6r_addr    02ccH       /* X6 register */
453
#pragma ADDRESS     y6r_addr    02ccH       /* Y6 register */
454
#pragma ADDRESS     x7r_addr    02ceH       /* X7 register */
455
#pragma ADDRESS     y7r_addr    02ceH       /* Y7 register */
456
#pragma ADDRESS     x8r_addr    02d0H       /* X8 register */
457
#pragma ADDRESS     y8r_addr    02d0H       /* Y8 register */
458
#pragma ADDRESS     x9r_addr    02d2H       /* X9 register */
459
#pragma ADDRESS     y9r_addr    02d2H       /* Y9 register */
460
#pragma ADDRESS     x10r_addr   02d4H       /* X10 register */
461
#pragma ADDRESS     y10r_addr   02d4H       /* Y10 register */
462
#pragma ADDRESS     x11r_addr   02d6H       /* X11 register */
463
#pragma ADDRESS     y11r_addr   02d6H       /* Y11 register */
464
#pragma ADDRESS     x12r_addr   02d8H       /* X12 register */
465
#pragma ADDRESS     y12r_addr   02d8H       /* Y12 register */
466
#pragma ADDRESS     x13r_addr   02daH       /* X13 register */
467
#pragma ADDRESS     y13r_addr   02daH       /* Y13 register */
468
#pragma ADDRESS     x14r_addr   02dcH       /* X14 register */
469
#pragma ADDRESS     y14r_addr   02dcH       /* Y14 register */
470
#pragma ADDRESS     x15r_addr   02deH       /* X15 register */
471
#pragma ADDRESS     y15r_addr   02deH       /* Y15 register */
472
#pragma ADDRESS     xyc_addr    02e0H       /* X-Y control register */
473

  
474

  
475
#pragma ADDRESS     u1smr4_addr 02e4H       /* UART1 special mode register 4 */
476
#pragma ADDRESS     u1smr3_addr 02e5H       /* UART1 special mode register 3 */
477
#pragma ADDRESS     u1smr2_addr 02e6H       /* UART1 special mode register 2 */
478
#pragma ADDRESS     u1smr_addr  02e7H       /* UART1 special mode register */
479
#pragma ADDRESS     u1mr_addr   02e8H       /* UART1 transmit/receive mode register */
480
#pragma ADDRESS     u1brg_addr  02e9H       /* UART1 bit rate generator */
481
#pragma ADDRESS     u1tb_addr   02eaH       /* UART1 transmit buffer register */
482
#pragma ADDRESS     u1c0_addr   02ecH       /* UART1 transmit/receive control register 0 */
483
#pragma ADDRESS     u1c1_addr   02edH       /* UART1 transmit/receive control register 1 */
484
#pragma ADDRESS     u1rb_addr   02eeH       /* UART1 receive buffer register */
485

  
486

  
487
#pragma ADDRESS     u4smr4_addr 02f4H       /* UART4 special mode register 4 */
488
#pragma ADDRESS     u4smr3_addr 02f5H       /* UART4 special mode register 3 */
489
#pragma ADDRESS     u4smr2_addr 02f6H       /* UART4 special mode register 2 */
490
#pragma ADDRESS     u4smr_addr  02f7H       /* UART4 special mode register */
491
#pragma ADDRESS     u4mr_addr   02f8H       /* UART4 transmit/receive mode register */
492
#pragma ADDRESS     u4brg_addr  02f9H       /* UART4 bit rate generator */
493
#pragma ADDRESS     u4tb_addr   02faH       /* UART4 transmit buffer register */
494
#pragma ADDRESS     u4c0_addr   02fcH       /* UART4 transmit/receive control register 0 */
495
#pragma ADDRESS     u4c1_addr   02fdH       /* UART4 transmit/receive control register 1 */
496
#pragma ADDRESS     u4rb_addr   02feH       /* UART4 receive buffer register */
497

  
498
#pragma ADDRESS     tbsr_addr   0300H       /* Timer B3,4,5 count start flag */
499

  
500
#pragma ADDRESS     ta11_addr   0302H       /* Timer A1-1 register */
501
#pragma ADDRESS     ta21_addr   0304H       /* Timer A2-1 register */
502
#pragma ADDRESS     ta41_addr   0306H       /* Timer A4-1 register */
503
#pragma ADDRESS     invc0_addr  0308H       /* Three-phase PWM control register 0 */
504
#pragma ADDRESS     invc1_addr  0309H       /* Three-phase PWM control register 1 */
505
#pragma ADDRESS     idb0_addr   030aH       /* Three-phase output buffer register 0 */
506
#pragma ADDRESS     idb1_addr   030bH       /* Three-phase output buffer register 1 */
507
#pragma ADDRESS     dtt_addr    030cH       /* Dead time timer */
508
#pragma ADDRESS     ictb2_addr  030dH       /* Timer B2 interrupt occurences frequency set counter */
509

  
510

  
511
#pragma ADDRESS     tb3_addr    0310H       /* Timer B3 register */
512
#pragma ADDRESS     tb4_addr    0312H       /* Timer B4 register */
513
#pragma ADDRESS     tb5_addr    0314H       /* Timer B5 register */
514

  
515

  
516
#pragma ADDRESS     tb3mr_addr  031bH       /* Timer B3 mode register */
517
#pragma ADDRESS     tb4mr_addr  031cH       /* Timer B4 mode register */
518
#pragma ADDRESS     tb5mr_addr  031dH       /* Timer B5 mode register */
519
#pragma ADDRESS     ifsra_addr  031eH       /* External interrupt request cause select register 1 */
520
#pragma ADDRESS     ifsr_addr   031fH       /* External interrupt request cause select register */
521

  
522

  
523
#pragma ADDRESS     u3smr4_addr 0324H       /* UART3 special mode register 4 */
524
#pragma ADDRESS     u3smr3_addr 0325H       /* UART3 special mode register 3 */
525
#pragma ADDRESS     u3smr2_addr 0326H       /* UART3 special mode register 2 */
526
#pragma ADDRESS     u3smr_addr  0327H       /* UART3 special mode register */
527
#pragma ADDRESS     u3mr_addr   0328H       /* UART3 transmit/receive mode register */
528
#pragma ADDRESS     u3brg_addr  0329H       /* UART3 bit rate generator */
529
#pragma ADDRESS     u3tb_addr   032aH       /* UART3 transmit buffer register */
530
#pragma ADDRESS     u3c0_addr   032cH       /* UART3 transmit/receive control register 0 */
531
#pragma ADDRESS     u3c1_addr   032dH       /* UART3 transmit/receive control register 1 */
532
#pragma ADDRESS     u3rb_addr   032eH       /* UART3 receive buffer register */
533

  
534

  
535
#pragma ADDRESS     u2smr4_addr 0334H       /* UART2 special mode register 4 */ 
536
#pragma ADDRESS     u2smr3_addr 0335H       /* UART2 special mode register 3 */ 
537
#pragma ADDRESS     u2smr2_addr 0336H       /* UART2 special mode register 2 */
538
#pragma ADDRESS     u2smr_addr  0337H       /* UART2 special mode register */
539
#pragma ADDRESS     u2mr_addr   0338H       /* UART2 transmit/receive mode register */
540
#pragma ADDRESS     u2brg_addr  0339H       /* UART2 bit rate generator */
541
#pragma ADDRESS     u2tb_addr   033aH       /* UART2 transmit buffer register */
542
#pragma ADDRESS     u2c0_addr   033cH       /* UART2 transmit/receive control register 0 */
543
#pragma ADDRESS     u2c1_addr   033dH       /* UART2 transmit/receive control register 1 */
544
#pragma ADDRESS     u2rb_addr   033eH       /* UART2 receive buffer register */
545
#pragma ADDRESS     tabsr_addr  0340H       /* Count start flag */
546
#pragma ADDRESS     cpsrf_addr  0341H       /* Clock prescaler reset flag */
547
#pragma ADDRESS     onsf_addr   0342H       /* One-shot start flag */
548
#pragma ADDRESS     trgsr_addr  0343H       /* Trigger select register */
549
#pragma ADDRESS     udf_addr    0344H       /* Up/down flag */
550

  
551
#pragma ADDRESS     ta0_addr    0346H       /* Timer A0 register */
552
#pragma ADDRESS     ta1_addr    0348H       /* Timer A1 register */
553
#pragma ADDRESS     ta2_addr    034aH       /* Timer A2 register */
554
#pragma ADDRESS     ta3_addr    034cH       /* Timer A3 register */
555
#pragma ADDRESS     ta4_addr    034eH       /* Timer A4 register */
556
#pragma ADDRESS     tb0_addr    0350H       /* Timer B0 register */
557
#pragma ADDRESS     tb1_addr    0352H       /* Timer B1 register */
558
#pragma ADDRESS     tb2_addr    0354H       /* Timer B2 register */
559
#pragma ADDRESS     ta0mr_addr  0356H       /* Timer A0 mode register */
560
#pragma ADDRESS     ta1mr_addr  0357H       /* Timer A1 mode register */
561
#pragma ADDRESS     ta2mr_addr  0358H       /* Timer A2 mode register */
562
#pragma ADDRESS     ta3mr_addr  0359H       /* Timer A3 mode register */
563
#pragma ADDRESS     ta4mr_addr  035aH       /* Timer A4 mode register */
564
#pragma ADDRESS     tb0mr_addr  035bH       /* Timer B0 mode register */
565
#pragma ADDRESS     tb1mr_addr  035cH       /* Timer B1 mode register */
566
#pragma ADDRESS     tb2mr_addr  035dH       /* Timer B2 mode register */
567
#pragma ADDRESS     tb2sc_addr  035eH       /* Timer B2 special mode register */
568
#pragma ADDRESS     tcspr_addr  035fH       /* Count source prescaler register */
569

  
570

  
571
#pragma ADDRESS     u0smr4_addr 0364H       /* UART0 special mode register 4 */ 
572
#pragma ADDRESS     u0smr3_addr 0365H       /* UART0 special mode register 3 */ 
573
#pragma ADDRESS     u0smr2_addr 0366H       /* UART0 special mode register 2 */
574
#pragma ADDRESS     u0smr_addr  0367H       /* UART0 special mode register */
575
#pragma ADDRESS     u0mr_addr   0368H       /* UART0 transmit/receive mode register */
576
#pragma ADDRESS     u0brg_addr  0369H       /* UART0 bit rate generator */
577
#pragma ADDRESS     u0tb_addr   036aH       /* UART0 transmit buffer register */
578
#pragma ADDRESS     u0c0_addr   036cH       /* UART0 transmit/receive control register 0 */
579
#pragma ADDRESS     u0c1_addr   036dH       /* UART0 transmit/receive control register 1 */
580
#pragma ADDRESS     u0rb_addr   036eH       /* UART0 receive buffer register */
581

  
582

  
583
#pragma ADDRESS     ircon_addr  0372H
584

  
585

  
586
#pragma ADDRESS     dm0sl_addr  0378H       /* DMA0 cause select register */
587
#pragma ADDRESS     dm1sl_addr  0379H       /* DMA1 cause select register */
588
#pragma ADDRESS     dm2sl_addr  037aH       /* DMA1 cause select register */
589
#pragma ADDRESS     dm3sl_addr  037bH       /* DMA1 cause select register */
590
#pragma ADDRESS     crcd_addr   037cH       /* CRC data register */
591
#pragma ADDRESS     crcin_addr  037eH       /* CRC input register */
592

  
593
#pragma ADDRESS     ad00_addr   0380H       /* A/D0 register 0 */
594
#pragma ADDRESS     ad01_addr   0382H       /* A/D0 register 1 */
595
#pragma ADDRESS     ad02_addr   0384H       /* A/D0 register 2 */
596
#pragma ADDRESS     ad03_addr   0386H       /* A/D0 register 3 */
597
#pragma ADDRESS     ad04_addr   0388H       /* A/D0 register 4 */
598
#pragma ADDRESS     ad05_addr   038aH       /* A/D0 register 5 */
599
#pragma ADDRESS     ad06_addr   038cH       /* A/D0 register 6 */
600
#pragma ADDRESS     ad07_addr   038eH       /* A/D0 register 7 */
601

  
602

  
603
#pragma ADDRESS     ad0con4_addr 0392H      /* A/D0 control register 4 */
604

  
605
#pragma ADDRESS     ad0con2_addr 0394H      /* A/D0 control register 2 */
606
#pragma ADDRESS     ad0con3_addr 0395H      /* A/D0 control register 3 */
607
#pragma ADDRESS     ad0con0_addr 0396H      /* A/D0 control register 0 */
608
#pragma ADDRESS     ad0con1_addr 0397H      /* A/D0 control register 1 */
609
#pragma ADDRESS     da0_addr    0398H       /* D/A register 0 */
610

  
611
#pragma ADDRESS     da1_addr    039aH       /* D/A register 1 */
612

  
613
#pragma ADDRESS     dacon_addr  039cH       /* D/A control register */
614
#pragma ADDRESS     dacon1_addr 039dH       /* D/A control register 1 */
615

  
616

  
617
#pragma ADDRESS     ps8_addr    03a0H       /* Function select register A8 */
618
#pragma ADDRESS     ps9_addr    03a1H       /* Function select register A9 */
619

  
620
#pragma ADDRESS     psl9_addr   03a3H       /* Function select register B9 */
621
#pragma ADDRESS     pse2_addr   03a4H       /* Function select register E2 */
622

  
623

  
624
#pragma ADDRESS     psd1_addr   03a7H       /* Function select register D1 */
625
#pragma ADDRESS     psd2_addr   03a8H       /* Function select register D2 */
626

  
627
#pragma ADDRESS     psc6_addr   03aaH       /* Function select register C6 */
628
#pragma ADDRESS     pse1_addr   03abH       /* Function select register E1 */
629
#pragma ADDRESS     psc2_addr   03acH       /* Function select register C2 */
630
#pragma ADDRESS     psc3_addr   03adH       /* Function select register C3 */
631

  
632
#pragma ADDRESS     psc_addr    03afH       /* Function select register C */
633
#pragma ADDRESS     ps0_addr    03b0H       /* Function select register A0 */
634
#pragma ADDRESS     ps1_addr    03b1H       /* Function select register A1 */
635
#pragma ADDRESS     psl0_addr   03b2H       /* Function select register B0 */
636
#pragma ADDRESS     psl1_addr   03b3H       /* Function select register B1 */
637
#pragma ADDRESS     ps2_addr    03b4H       /* Function select register A2 */
638
#pragma ADDRESS     ps3_addr    03b5H       /* Function select register A3 */
639
#pragma ADDRESS     psl2_addr   03b6H       /* Function select register B2 */
640
#pragma ADDRESS     psl3_addr   03b7H       /* Function select register B3 */
641
#pragma ADDRESS     ps4_addr    03b8H       /* Function select register A4 */
642
#pragma ADDRESS     ps5_addr    03b9H       /* Function select register A5 */
643

  
644

  
645
#pragma ADDRESS     ps6_addr    03bcH       /* Function select register A6 */
646
#pragma ADDRESS     ps7_addr    03bdH       /* Function select register A7 */
647
#pragma ADDRESS     psl6_addr   03beH       /* Function select register B6 */
648

  
649
#pragma ADDRESS     p6_addr     03c0H       /* Port P6 register */
650
#pragma ADDRESS     p7_addr     03c1H       /* Port P7 register */
651
#pragma ADDRESS     pd6_addr    03c2H       /* Port P6 direction register */
652
#pragma ADDRESS     pd7_addr    03c3H       /* Port P7 direction register */
653
#pragma ADDRESS     p8_addr     03c4H       /* Port P8 register */
654
#pragma ADDRESS     p9_addr     03c5H       /* Port P9 register */
655
#pragma ADDRESS     pd8_addr    03c6H       /* Port P8 direction register */
656
#pragma ADDRESS     pd9_addr    03c7H       /* Port P9 direction register */
657
#pragma ADDRESS     p10_addr    03c8H       /* Port P10 register */
658
#pragma ADDRESS     p11_addr    03c9H       /* Port P11 register */
659
#pragma ADDRESS     pd10_addr   03caH       /* Port P10 direction register */
660
#pragma ADDRESS     pd11_addr   03cbH       /* Port P11 direction register */
661
#pragma ADDRESS     p12_addr    03ccH       /* Port P12 register */
662
#pragma ADDRESS     p13_addr    03cdH       /* Port P13 register */
663
#pragma ADDRESS     pd12_addr   03ceH       /* Port P12 direction register */
664
#pragma ADDRESS     pd13_addr   03cfH       /* Port P13 direction register */
665
#pragma ADDRESS     p14_addr    03d0H       /* Port P14 register */
666
#pragma ADDRESS     p15_addr    03d1H       /* Port P15 register */
667
#pragma ADDRESS     pd14_addr   03d2H       /* Port P14 direction register */
668
#pragma ADDRESS     pd15_addr   03d3H       /* Port P15 direction register */
669

  
670

  
671
#pragma ADDRESS     pur2_addr   03daH       /* Pull-up control register 2 */
672
#pragma ADDRESS     pur3_addr   03dbH       /* Pull-up control register 3 */
673
#pragma ADDRESS     pur4_addr   03dcH       /* Pull-up control register 4 */
674

  
675

  
676
#pragma ADDRESS     p0_addr     03e0H       /* Port P0 register */
677
#pragma ADDRESS     p1_addr     03e1H       /* Port P1 register */
678
#pragma ADDRESS     pd0_addr    03e2H       /* Port P0 direction register */
679
#pragma ADDRESS     pd1_addr    03e3H       /* Port P1 direction register */
680
#pragma ADDRESS     p2_addr     03e4H       /* Port P2 register */
681
#pragma ADDRESS     p3_addr     03e5H       /* Port P3 register */
682
#pragma ADDRESS     pd2_addr    03e6H       /* Port P2 direction register */
683
#pragma ADDRESS     pd3_addr    03e7H       /* Port P3 direction register */
684
#pragma ADDRESS     p4_addr     03e8H       /* Port P4 register */
685
#pragma ADDRESS     p5_addr     03e9H       /* Port P5 register */
686
#pragma ADDRESS     pd4_addr    03eaH       /* Port P4 direction register */
687
#pragma ADDRESS     pd5_addr    03ebH       /* Port P5 direction register */
688

  
689

  
690
#pragma ADDRESS     pur0_addr   03f0H       /* Pull-up control register 0 */
691
#pragma ADDRESS     pur1_addr   03f1H       /* Pull-up control register 1 */
692

  
693

  
694
#pragma ADDRESS     pcr_addr    03ffH       /* Port control register */
695

  
696

  
697
/*******************************************************
698
*   declare  SFR char                                   *
699
********************************************************/
700
unsigned char   da0_addr;               /* D/A register 0 */
701
#define     da0     da0_addr
702

  
703
unsigned char   da1_addr;               /* D/A register 1 */
704
#define     da1     da1_addr
705

  
706
/********************************************************
707
*   declare  SFR short                                  *
708
********************************************************/
709
/*---------------------------------------------------------------------
710
    Timer registers ; Read and write to this register in 16-bit units.
711
-----------------------------------------------------------------------*/
712
unsigned short   ta11_addr;             /* Timer A1-1 register */
713
#define     ta11     ta11_addr
714

  
715
unsigned short   ta21_addr;             /* Timer A2-1 register */
716
#define     ta21     ta21_addr
717

  
718
unsigned short   ta41_addr;             /* Timer A4-1 register */
719
#define     ta41     ta41_addr
720

  
721
unsigned short   tb3_addr;              /* Timer B3 register */
722
#define     tb3     tb3_addr
723

  
724
unsigned short   tb4_addr;              /* Timer B4 register */
725
#define     tb4     tb4_addr
726

  
727
unsigned short   tb5_addr;              /* Timer B5 register */
728
#define     tb5     tb5_addr
729

  
730
unsigned short   ta0_addr;              /* Timer A0 register */
731
#define     ta0     ta0_addr
732

  
733
unsigned short   ta1_addr;              /* Timer A1 register */
734
#define     ta1     ta1_addr
735

  
736
unsigned short   ta2_addr;              /* Timer A2 register */
737
#define     ta2     ta2_addr
738

  
739
unsigned short   ta3_addr;              /* Timer A3 register */
740
#define     ta3     ta3_addr
741

  
742
unsigned short   ta4_addr;              /* Timer A4 register */
743
#define     ta4     ta4_addr
744

  
745
unsigned short   tb0_addr;              /* Timer B0 register */
746
#define     tb0     tb0_addr
747

  
748
unsigned short   tb1_addr;              /* Timer B1 register */
749
#define     tb1     tb1_addr
750

  
751
unsigned short   tb2_addr;              /* Timer B2 register */
752
#define     tb2     tb2_addr
753

  
754
/*---------------------------------------------------------------------
755
    IIO registers ; Read and write to this register in 16-bit units.
756
-----------------------------------------------------------------------*/
757

  
758
/********************************************************
759
*   group 0 and 1 and 2                                 *
760
********************************************************/
761
#define     g1bt        g1bt_addr.word        /* Base Timer Register 1 */
762
#define     g1btl       g1bt_addr.byte.low
763
#define     g1bth       g1bt_addr.byte.high
764

  
765
#define     g1tm0        g1tm0_addr.word      /* Time Measurement Register 10 */
766
#define     g1tm0l       g1tm0_addr.byte.low
767
#define     g1tm0h       g1tm0_addr.byte.high
768

  
769
#define     g1tm1        g1tm1_addr.word      /* Time Measurement Register 11 */
770
#define     g1tm1l       g1tm1_addr.byte.low
771
#define     g1tm1h       g1tm1_addr.byte.high
772

  
773
#define     g1tm2        g1tm2_addr.word      /* Time Measurement Register 12 */
774
#define     g1tm2l       g1tm2_addr.byte.low
775
#define     g1tm2h       g1tm2_addr.byte.high
776

  
777
#define     g1tm3        g1tm3_addr.word      /* Time Measurement Register 13 */
778
#define     g1tm3l       g1tm3_addr.byte.low
779
#define     g1tm3h       g1tm3_addr.byte.high
780

  
781
#define     g1tm4        g1tm4_addr.word      /* Time Measurement Register 14 */
782
#define     g1tm4l       g1tm4_addr.byte.low
783
#define     g1tm4h       g1tm4_addr.byte.high
784

  
785
#define     g1tm5        g1tm5_addr.word      /* Time Measurement Register 15 */
786
#define     g1tm5l       g1tm5_addr.byte.low
787
#define     g1tm5h       g1tm5_addr.byte.high
788

  
789
#define     g1tm6        g1tm6_addr.word      /* Time Measurement Register 16 */
790
#define     g1tm6l       g1tm6_addr.byte.low
791
#define     g1tm6h       g1tm6_addr.byte.high
792

  
793
#define     g1tm7        g1tm7_addr.word      /* Time Measurement Register 17 */
794
#define     g1tm7l       g1tm7_addr.byte.low
795
#define     g1tm7h       g1tm7_addr.byte.high
796

  
797
#define     g1po0        g1po0_addr.word      /* Waveform Generate Register 10 */
798
#define     g1po0l       g1po0_addr.byte.low
799
#define     g1po0h       g1po0_addr.byte.high
800

  
801
#define     g1po1        g1po1_addr.word      /* Waveform Generate Register 11 */
802
#define     g1po1l       g1po1_addr.byte.low
803
#define     g1po1h       g1po1_addr.byte.high
804

  
805
#define     g1po2        g1po2_addr.word      /* Waveform Generate Register 12 */
806
#define     g1po2l       g1po2_addr.byte.low
807
#define     g1po2h       g1po2_addr.byte.high
808

  
809
#define     g1po3        g1po3_addr.word      /* Waveform Generate Register 13 */
810
#define     g1po3l       g1po3_addr.byte.low
811
#define     g1po3h       g1po3_addr.byte.high
812

  
813
#define     g1po4        g1po4_addr.word      /* Waveform Generate Register 14 */
814
#define     g1po4l       g1po4_addr.byte.low
815
#define     g1po4h       g1po4_addr.byte.high
816

  
817
#define     g1po5        g1po5_addr.word      /* Waveform Generate Register 15 */
818
#define     g1po5l       g1po5_addr.byte.low
819
#define     g1po5h       g1po5_addr.byte.high
820

  
821
#define     g1po6        g1po6_addr.word      /* Waveform Generate Register 16 */
822
#define     g1po6l       g1po6_addr.byte.low
823
#define     g1po6h       g1po6_addr.byte.high
824

  
825
#define     g1po7        g1po7_addr.word      /* Waveform Generate Register 17 */
826
#define     g1po7l       g1po7_addr.byte.low
827
#define     g1po7h       g1po7_addr.byte.high
828

  
829
#define     g2bt         g2bt_addr.word        /* Base Timer Register 2 */
830
#define     g2btl        g2bt_addr.byte.low
831
#define     g2bth        g2bt_addr.byte.high
832

  
833
#define     g2po0        g2po0_addr.word      /* Waveform Generate Register 20 */
834
#define     g2po0l       g2po0_addr.byte.low
835
#define     g2po0h       g2po0_addr.byte.high
836

  
837
#define     g2po1        g2po1_addr.word      /* Waveform Generate Register 21 */
838
#define     g2po1l       g2po1_addr.byte.low
839
#define     g2po1h       g2po1_addr.byte.high
840

  
841
#define     g2po2        g2po2_addr.word      /* Waveform Generate Register 22 */
842
#define     g2po2l       g2po2_addr.byte.low
843
#define     g2po2h       g2po2_addr.byte.high
844

  
845
#define     g2po3        g2po3_addr.word      /* Waveform Generate Register 23 */
846
#define     g2po3l       g2po3_addr.byte.low
847
#define     g2po3h       g2po3_addr.byte.high
848

  
849
#define     g2po4        g2po4_addr.word      /* Waveform Generate Register 24 */
850
#define     g2po4l       g2po4_addr.byte.low
851
#define     g2po4h       g2po4_addr.byte.high
852

  
853
#define     g2po5        g2po5_addr.word      /* Waveform Generate Register 25 */
854
#define     g2po5l       g2po5_addr.byte.low
855
#define     g2po5h       g2po5_addr.byte.high
856

  
857
#define     g2po6        g2po6_addr.word      /* Waveform Generate Register 26 */
858
#define     g2po6l       g2po6_addr.byte.low
859
#define     g2po6h       g2po6_addr.byte.high
860

  
861
#define     g2po7        g2po7_addr.word      /* Waveform Generate Register 27 */
862
#define     g2po7l       g2po7_addr.byte.low
863
#define     g2po7h       g2po7_addr.byte.high
864

  
865
#define     g0tcrc        g0tcrc_addr.word      /* Transmit CRC Code Register 0 */
866
#define     g0tcrcl       g0tcrc_addr.byte.low
867
#define     g0tcrch       g0tcrc_addr.byte.high
868

  
869
#define     g1tcrc        g1tcrc_addr.word      /* Transmit CRC Code Register 1 */
870
#define     g1tcrcl       g1tcrc_addr.byte.low
871
#define     g1tcrch       g1tcrc_addr.byte.high
872

  
873
#define     g0rcrc        g0rcrc_addr.word      /* Receive CRC Code Register 0 */
874
#define     g0rcrcl       g0rcrc_addr.byte.low
875
#define     g0rcrch       g0rcrc_addr.byte.high
876

  
877
#define     g1rcrc        g1rcrc_addr.word      /* Receive CRC Code Register 1 */
878
#define     g1rcrcl       g1rcrc_addr.byte.low
879
#define     g1rcrch       g1rcrc_addr.byte.high
880

  
881
/*------------------------------------------------------
882
    SI/O receive buffer register
883
------------------------------------------------------*/
884

  
885
/*------------------------------------------------------
886
     SI/O Receive Buffer Register 0
887
------------------------------------------------------*/
888
#define     g0rb        g0rb_addr.word
889
#define     g0rbl       g0rb_addr.byte.low
890
#define     g0rbh       g0rb_addr.byte.high
891
#define     oer_g0rb    g0rb_addr.bit.b12   /* Overrun error flag */
892
#define     fer_g0rb    g0rb_addr.bit.b13   /* Framing error flag */
893

  
894
/*------------------------------------------------------
895
     SI/O Receive Buffer Register 1
896
------------------------------------------------------*/
897
#define     g1rb        g1rb_addr.word
898
#define     g1rbl       g1rb_addr.byte.low
899
#define     g1rbh       g1rb_addr.byte.high
900
#define     oer_g1rb    g1rb_addr.bit.b12       /* Overrun error flag */
901
#define     fer_g1rb    g1rb_addr.bit.b13       /* Framing error flag */
902

  
903
/*------------------------------------------------------
904
     SI/O Receive Buffer Register 2
905
------------------------------------------------------*/
906
#define     g2rb        g2rb_addr.word
907
#define     g2rbl       g2rb_addr.byte.low
908
#define     g2rbh       g2rb_addr.byte.high
909
#define     oer_g2rb    g2rb_addr.bit.b12       /* Overrun error flag */
910

  
911
/*------------------------------------------------------
912
     SI/O Transmit Buffer Register 2
913
------------------------------------------------------*/
914
#define     g2tb        g2tb_addr.word
915
#define     g2tbl       g2tb_addr.byte.low
916
#define     g2tbh       g2tb_addr.byte.high
917
#define     a_g2tb      g2tb_addr.bit.b13
918
#define     pc_g2tb     g2tb_addr.bit.b14
919
#define     p_g2tb      g2tb_addr.bit.b15
920

  
921
/*------------------------------------------------------
922

  
923
------------------------------------------------------*/
924
#define     iear        iear_addr.word
925
#define     iearl       iear_addr.byte.low
926
#define     iearh       iear_addr.byte.high
927

  
928
/********************************************************
929
*   declare SFR bit                                     *
930
********************************************************/
931
struct bit_def {
932
        char    b0:1;
933
        char    b1:1;
934
        char    b2:1;
935
        char    b3:1;
936
        char    b4:1;
937
        char    b5:1;
938
        char    b6:1;
939
        char    b7:1;
940
};
941
union byte_def{
942
    struct bit_def bit;
943
    char    byte;
944
};
945

  
946
/*------------------------------------------------------
947
    External Space Wait Control Register 0
948
------------------------------------------------------*/
949
union byte_def ewcr0_addr;
950
#define     ewcr0      ewcr0_addr.byte
951

  
952
#define     ewcr000    ewcr0_addr.bit.b0    /* (b4-b0) Bus cycle select bit */
953
#define     ewcr001    ewcr0_addr.bit.b1
954
#define     ewcr002    ewcr0_addr.bit.b2
955
#define     ewcr003    ewcr0_addr.bit.b3
956
#define     ewcr004    ewcr0_addr.bit.b4
957
                                            /* (b5) Nothing is assigned */
958
#define     ewcr006    ewcr0_addr.bit.b6    /* Recovery cycle addition select bit */
959
                                            /* (b7) Nothing is assigned */
960

  
961
/*------------------------------------------------------
962
    External Space Wait Control Register 1
963
------------------------------------------------------*/
964
union byte_def ewcr1_addr;
965
#define     ewcr1      ewcr1_addr.byte
966

  
967
#define     ewcr100    ewcr1_addr.bit.b0    /* (b4-b0) Bus cycle select bit */
968
#define     ewcr101    ewcr1_addr.bit.b1
969
#define     ewcr102    ewcr1_addr.bit.b2
970
#define     ewcr103    ewcr1_addr.bit.b3
971
#define     ewcr104    ewcr1_addr.bit.b4
972
                                            /* (b5) Nothing is assigned */
973
#define     ewcr106    ewcr1_addr.bit.b6    /* Recovery cycle addition select bit */
974
                                            /* (b7) Nothing is assigned */
975

  
976
/*------------------------------------------------------
977
    External Space Wait Control Register 2
978
------------------------------------------------------*/
979
union byte_def ewcr2_addr;
980
#define     ewcr2      ewcr2_addr.byte
981

  
982
#define     ewcr200    ewcr2_addr.bit.b0    /* (b4-b0) Bus cycle select bit */
983
#define     ewcr201    ewcr2_addr.bit.b1
984
#define     ewcr202    ewcr2_addr.bit.b2
985
#define     ewcr203    ewcr2_addr.bit.b3
986
#define     ewcr204    ewcr2_addr.bit.b4
987
                                            /* (b5) Nothing is assigned */
988
#define     ewcr206    ewcr2_addr.bit.b6    /* Recovery cycle addition select bit */
989
                                            /* (b7) Nothing is assigned */
990

  
991
/*------------------------------------------------------
992
    External Space Wait Control Register 3
993
------------------------------------------------------*/
994
union byte_def ewcr3_addr;
995
#define     ewcr3      ewcr3_addr.byte
996

  
997
#define     ewcr300    ewcr3_addr.bit.b0    /* (b4-b0) Bus cycle select bit */
998
#define     ewcr301    ewcr3_addr.bit.b1
999
#define     ewcr302    ewcr3_addr.bit.b2
1000
#define     ewcr303    ewcr3_addr.bit.b3
1001
#define     ewcr304    ewcr3_addr.bit.b4
1002
                                            /* (b5) Nothing is assigned */
1003
#define     ewcr306    ewcr3_addr.bit.b6    /* Recovery cycle addition select bit */
1004
                                            /* (b7) Nothing is assigned */
1005

  
1006
/*------------------------------------------------------
1007
    Flash Memory control register 1
1008
------------------------------------------------------*/
1009
union byte_def fmr1_addr;
1010
#define     fmr1      fmr1_addr.byte
1011
                                            /* (b0) Reserved bit */
1012
#define     fmr11     fmr1_addr.bit.b1      /* EW1 mode select bit */
1013
                                            /* (b3-b2) Reserved bit */
1014
                                            /* (b5-b4) Reserved bit */
1015
#define     fmr16     fmr1_addr.bit.b6      /* Lock bit status flag */
1016
                                            /* (b7) Reserved bit (Set to 0) */
1017

  
1018
/*------------------------------------------------------
1019
    Flash Memory control register 0
1020
------------------------------------------------------*/
1021
#define     fmr       fmr_addr.word
1022

  
1023
union byte_def fmr0_addr;
1024
#define     fmr0      fmr0_addr.byte
1025

  
1026
#define     fmr00     fmr0_addr.bit.b0      /* RY/BY status flag */
1027
#define     fmr01     fmr0_addr.bit.b1      /* CPU rewrite mode select bit */
1028
#define     fmr02     fmr0_addr.bit.b2      /* Lock bit disable select bit */
1029
#define     fmstp     fmr0_addr.bit.b3      /* Flash memory stop bit */
1030
                                            /* (b4) Reserved bit (Set to 0) */
1031
#define     fmr05     fmr0_addr.bit.b5      /* User ROM area select bit (Available in boot mode only) */
1032
#define     fmr06     fmr0_addr.bit.b6      /* Program status flag */
1033
#define     fmr07     fmr0_addr.bit.b7      /* Erase status flag */
1034

  
1035
/*------------------------------------------------------
1036
    Processor mode register 0
1037
------------------------------------------------------*/
1038
union byte_def pm0_addr;
1039
#define     pm0     pm0_addr.byte
1040

  
1041
#define     pm00        pm0_addr.bit.b0     /* Processor mode bit */
1042
#define     pm01        pm0_addr.bit.b1     /* Processor mode bit */
1043
#define     pm02        pm0_addr.bit.b2     /* R/W mode select bit */
1044
#define     pm03        pm0_addr.bit.b3     /* Software reset bit */
1045
#define     pm04        pm0_addr.bit.b4     /* Multiplexed bus space select bit */
1046
#define     pm05        pm0_addr.bit.b5     /* Multiplexed bus space select bit */
1047
                                            /* (b6) Reserved bit (Set to 0) */
1048
#define     pm07        pm0_addr.bit.b7     /* BCLK output function select bit */
1049

  
1050
/*------------------------------------------------------
1051
    Processor mode register 1
1052
------------------------------------------------------*/
1053
union byte_def pm1_addr;
1054
#define     pm1     pm1_addr.byte
1055

  
1056
#define     pm10        pm1_addr.bit.b0     /* External memory area mode bit */
1057
#define     pm11        pm1_addr.bit.b1     /* External memory area mode bit */
1058
#define     pm12        pm1_addr.bit.b2     /* Internal memory wait bit */
1059
#define     pm13        pm1_addr.bit.b3     /* SFR wait bit */
1060
#define     pm14        pm1_addr.bit.b4     /* ALE pin select bit */
1061
#define     pm15        pm1_addr.bit.b5     /* ALE pin select bit */
1062
                                            /* (b7-b6) Reserved bit (Set to 0) */
1063

  
1064
/*------------------------------------------------------
1065
    Processor mode register 2
1066
------------------------------------------------------*/
1067
union byte_def pm2_addr;
1068
#define     pm2     pm2_addr.byte
1069
                                            /* (b0) Reserved bit (Set to 0) */
1070
#define     pm21        pm2_addr.bit.b1     /* System clock protect bit */
1071
#define     pm22        pm2_addr.bit.b2     /* WDT count source protect bit */
1072
                                            /* (b5-b3) Reserved bit (Set to 0) */
1073
#define     pm26        pm2_addr.bit.b6     /* (b7-b6) f2n count source select bit */
1074
#define     pm27        pm2_addr.bit.b7
1075

  
1076
/*------------------------------------------------------
1077
    System clock control register 0
1078
------------------------------------------------------*/
1079
union byte_def cm0_addr;
1080
#define     cm0     cm0_addr.byte
1081

  
1082
#define     cm00        cm0_addr.bit.b0     /* Clock output function select bit */
1083
#define     cm01        cm0_addr.bit.b1     /* Clock output function select bit */
1084
#define     cm02        cm0_addr.bit.b2     /* WAIT peripheral function clock stop bit */
1085
#define     cm03        cm0_addr.bit.b3     /* Xcin-Xcout drive capacity select bit */
1086
#define     cm04        cm0_addr.bit.b4     /* Port Xc select bit */
1087
#define     cm05        cm0_addr.bit.b5     /* Main clock stop bit */
1088
#define     cm06        cm0_addr.bit.b6     /* WDT function select bit */
1089
#define     cm07        cm0_addr.bit.b7     /* CPU clock select bit0 */
1090

  
1091
/*------------------------------------------------------
1092
    System clock control register 1
1093
------------------------------------------------------*/
1094
union byte_def cm1_addr;
1095
#define     cm1     cm1_addr.byte
1096

  
1097
#define     cm10        cm1_addr.bit.b0     /* All clock stop control bit */
1098
                                            /* (b4-b1) Reserved bit (Set to 0) */
1099
                                            /* (b5) Reserved bit (Set to 1) */
1100
                                            /* (b6) Reserved bit (Set to 0) */
1101
#define     cm17        cm1_addr.bit.b7     /* CPU clock select bit1 */
1102

  
1103
/*------------------------------------------------------
1104
    Oscillation stop detect register
1105
------------------------------------------------------*/
1106
union byte_def cm2_addr;
1107
#define     cm2     cm2_addr.byte
1108

  
1109
#define     cm20        cm2_addr.bit.b0     /* Oscillation stop detect enable bit */
1110
#define     cm21        cm2_addr.bit.b1     /* CPU clock select bit2 */
1111
#define     cm22        cm2_addr.bit.b2     /* Oscillation stop detect flag */
1112
#define     cm23        cm2_addr.bit.b3     /* Main clock monitor flag */
1113
                                            /* (b7-b4) Reserved bit (Set to 0) */
1114

  
1115

  
1116
/*------------------------------------------------------
1117
    Address match interrupt enable register
1118
------------------------------------------------------*/
1119
union byte_def aier_addr;
1120
#define     aier        aier_addr.byte
1121

  
1122
#define     aier0       aier_addr.bit.b0    /* Address match interrupt 0 enable bit */
1123
#define     aier1       aier_addr.bit.b1    /* Address match interrupt 1 enable bit */
1124
#define     aier2       aier_addr.bit.b2    /* Address match interrupt 2 enable bit */
1125
#define     aier3       aier_addr.bit.b3    /* Address match interrupt 3 enable bit */
1126
#define     aier4       aier_addr.bit.b4    /* Address match interrupt 4 enable bit */
1127
#define     aier5       aier_addr.bit.b5    /* Address match interrupt 5 enable bit */
1128
#define     aier6       aier_addr.bit.b6    /* Address match interrupt 6 enable bit */
1129
#define     aier7       aier_addr.bit.b7    /* Address match interrupt 7 enable bit */
1130

  
1131
/*------------------------------------------------------
1132
    X-Y control register
1133
------------------------------------------------------*/
1134
union byte_def xyc_addr;
1135
#define     xyc     xyc_addr.byte
1136

  
1137
#define     xyc0        xyc_addr.bit.b0     /* Read-mode set bit */
1138
#define     xyc1        xyc_addr.bit.b1     /* Write-mode set bit */
1139
                                            /* (b7-b2) Nothing is assigned */
1140

  
1141
/*------------------------------------------------------
1142
    Protect register
1143
------------------------------------------------------*/
1144
union byte_def prcr_addr;
1145
#define     prcr        prcr_addr.byte
1146

  
1147
#define     prc0        prcr_addr.bit.b0    /* Protect bit0 */
1148
#define     prc1        prcr_addr.bit.b1    /* Protect bit1 */
1149
#define     prc2        prcr_addr.bit.b2    /* Protect bit2 */
1150
#define     prc3        prcr_addr.bit.b3    /* Protect bit3 */
1151
                                            /* (b7-b4) Nothing is assigned */
1152

  
1153
/*------------------------------------------------------
1154
    External data bus width control register
1155
------------------------------------------------------*/
1156
union byte_def ds_addr;
1157
#define     ds      ds_addr.byte
1158

  
1159
#define     ds0     ds_addr.bit.b0          /* External space 0 data bus width select bit */
1160
#define     ds1     ds_addr.bit.b1          /* External space 1 data bus width select bit */
1161
#define     ds2     ds_addr.bit.b2          /* External space 2 data bus width select bit */
1162
#define     ds3     ds_addr.bit.b3          /* External space 3 data bus width select bit */
1163
                                            /* (b7-b4) Nothing is assigned */
1164

  
1165
/*------------------------------------------------------
1166
    Main clock division register
1167
------------------------------------------------------*/
1168
union byte_def mcd_addr;
1169
#define     mcd     mcd_addr.byte
1170

  
1171
#define     mcd0        mcd_addr.bit.b0     /* (b4-b0) Main clock division select bit */
1172
#define     mcd1        mcd_addr.bit.b1
1173
#define     mcd2        mcd_addr.bit.b2
1174
#define     mcd3        mcd_addr.bit.b3
1175
#define     mcd4        mcd_addr.bit.b4
1176
                                            /* (b7-b5) Reserved bit (Set to 0) */
1177

  
1178
/*------------------------------------------------------
1179
   Count source prescaler register
1180
------------------------------------------------------*/
1181
union byte_def tcspr_addr;
1182
#define     tcspr     tcspr_addr.byte
1183

  
1184
#define     cnt0        tcspr_addr.bit.b0   /* (b3-b0) Divide ratio select bit */
1185
#define     cnt1        tcspr_addr.bit.b1
1186
#define     cnt2        tcspr_addr.bit.b2
1187
#define     cnt3        tcspr_addr.bit.b3
1188
                                            /* (b6-b4) Reserved bit (Set to 0) */
1189
#define     cst         tcspr_addr.bit.b7   /* Operation enable bit */
1190

  
1191
/*------------------------------------------------------
1192
    Exit priority register
1193
------------------------------------------------------*/
1194
union byte_def rlvl_addr;
1195
#define     rlvl        rlvl_addr.byte
1196

  
1197
#define     rlvl0       rlvl_addr.bit.b0    /* (b2-b0) Interrupt priority set bits to exit STOP/WAIT mode */
1198
#define     rlvl1       rlvl_addr.bit.b1
1199
#define     rlvl2       rlvl_addr.bit.b2
1200
#define     fsit        rlvl_addr.bit.b3    /* High-speed interrupt set bit */
1201
                                            /* (b4) Nothing is assigned */
1202
#define     dmaii       rlvl_addr.bit.b5    /* DMAC II select bit */
1203
                                            /* (b7-b6) Nothing is assigned */
1204

  
1205
/*------------------------------------------------------
1206
    External interrupt request cause select register 1
1207
------------------------------------------------------*/
1208
union byte_def ifsra_addr;
1209
#define     ifsra        ifsra_addr.byte
1210

  
1211
#define     ifsr10      ifsra_addr.bit.b0   /* INT6 interrupt polarity select bit */
1212
#define     ifsr11      ifsra_addr.bit.b1   /* INT7 interrupt polarity select bit */
1213
#define     ifsr12      ifsra_addr.bit.b2   /* INT8 interrupt polarity select bit */
1214
                                            /* (b7-b3) Reserved bit (Set to 0) */
1215

  
1216
/*------------------------------------------------------
1217
    External interrupt request cause select register
1218
------------------------------------------------------*/
1219
union byte_def ifsr_addr;
1220
#define     ifsr        ifsr_addr.byte
1221

  
1222
#define     ifsr0       ifsr_addr.bit.b0    /* INT0 interrupt polarity select bit */
1223
#define     ifsr1       ifsr_addr.bit.b1    /* INT1 interrupt polarity select bit */
1224
#define     ifsr2       ifsr_addr.bit.b2    /* INT2 interrupt polarity select bit */
1225
#define     ifsr3       ifsr_addr.bit.b3    /* INT3 interrupt polarity select bit */
1226
#define     ifsr4       ifsr_addr.bit.b4    /* INT4 interrupt polarity select bit */
1227
#define     ifsr5       ifsr_addr.bit.b5    /* INT5 interrupt polarity select bit */
1228
#define     ifsr6       ifsr_addr.bit.b6    /* UART0,3 interrupt cause select bit */
1229
#define     ifsr7       ifsr_addr.bit.b7    /* UART1,4 interrupt cause select bit */
1230

  
1231
/*------------------------------------------------------
1232
    Timer B2 special mode register
1233
------------------------------------------------------*/
1234
union byte_def tb2sc_addr;
1235
#define     tb2sc     tb2sc_addr.byte
1236

  
1237
#define     pwcon     tb2sc_addr.bit.b0     /* Timer B2 reload timing switching bit */
1238
                                            /* (b7-b1) Nothing is assigned */
1239

  
1240
/*------------------------------------------------------
1241
    Watchdog timer start register
1242
------------------------------------------------------*/
1243
union byte_def wdts_addr;
1244
#define     wdts        wdts_addr.byte
1245

  
1246
/*------------------------------------------------------
1247
    CRC input register
1248
------------------------------------------------------*/
1249
union byte_def crcin_addr;
1250
#define     crcin       crcin_addr.byte
1251

  
1252
/*------------------------------------------------------
1253
    Watchdog timer control register
1254
------------------------------------------------------*/
1255
union byte_def wdc_addr;
1256
#define     wdc     wdc_addr.byte
1257

  
1258
                                            /* (b4-b0) High-order bits of the watchdog timer */
1259
#define     wdc5        wdc_addr.bit.b5     /* Cold start/warm start detect flag */
1260
                                            /* (b6) Reserved bit (Set to 0) */
1261
#define     wdc7        wdc_addr.bit.b7     /* Prescaler select bit */
1262

  
1263
/*------------------------------------------------------
1264
    Voltage detection register 1
1265
------------------------------------------------------*/
1266
union byte_def vcr1_addr;
1267
#define     vcr1     vcr1_addr.byte
1268
                                            /* (b2-b0) Reserved bit (Set to 0) */
1269
#define     vc13        vcr1_addr.bit.b3    /* Voltage down monitor flag */
1270
                                            /* (b7-b4) Reserved bit (Set to 0) */
1271

  
1272
/*------------------------------------------------------
1273
    Voltage detection register 2
1274
------------------------------------------------------*/
1275
union byte_def vcr2_addr;
1276
#define     vcr2     vcr2_addr.byte
1277
                                            /* (b5-b0) Reserved bit (Set to 0) */
1278
#define     vc26        vcr2_addr.bit.b6    /* Reset level monitor bit */
1279
#define     vc27        vcr2_addr.bit.b7    /* Voltage down monitor bit */
1280

  
1281
/*------------------------------------------------------
1282
    Count start flag
1283
------------------------------------------------------*/
1284
union byte_def tabsr_addr;
1285
#define     tabsr       tabsr_addr.byte
1286

  
1287
#define     ta0s        tabsr_addr.bit.b0   /* Timer A0 count start flag */
1288
#define     ta1s        tabsr_addr.bit.b1   /* Timer A1 count start flag */
1289
#define     ta2s        tabsr_addr.bit.b2   /* Timer A2 count start flag */
1290
#define     ta3s        tabsr_addr.bit.b3   /* Timer A3 count start flag */
1291
#define     ta4s        tabsr_addr.bit.b4   /* Timer A4 count start flag */
1292
#define     tb0s        tabsr_addr.bit.b5   /* Timer B0 count start flag */
1293
#define     tb1s        tabsr_addr.bit.b6   /* Timer B1 count start flag */
1294
#define     tb2s        tabsr_addr.bit.b7   /* Timer B2 count start flag */
1295

  
1296
/*------------------------------------------------------
1297
    Timer B3,4,5 count start flag
1298
------------------------------------------------------*/
1299
union byte_def tbsr_addr;
1300
#define     tbsr        tbsr_addr.byte
1301
                                            /* (b4-b0) Nothing is assigned */
1302
#define     tb3s        tbsr_addr.bit.b5    /* Timer B3 count start flag */
1303
#define     tb4s        tbsr_addr.bit.b6    /* Timer B4 count start flag */
1304
#define     tb5s        tbsr_addr.bit.b7    /* Timer B5 count start flag */
1305

  
1306
/*------------------------------------------------------
1307
    Three-phase PWM control register 0
1308
------------------------------------------------------*/
1309
union byte_def invc0_addr;
1310
#define     invc0       invc0_addr.byte
1311

  
1312
#define     inv00       invc0_addr.bit.b0   /* Interrupt enable output polarity select bit */
1313
#define     inv01       invc0_addr.bit.b1   /* Interrupt enable output specification bit */
1314
#define     inv02       invc0_addr.bit.b2   /* Mode select bit */
1315
#define     inv03       invc0_addr.bit.b3   /* Output control bit */
1316
#define     inv04       invc0_addr.bit.b4   /* Positive & negative phases concurrent active disable function enable bit */
1317
#define     inv05       invc0_addr.bit.b5   /* Positive & negative phases concurrent active output detect flag */
1318
#define     inv06       invc0_addr.bit.b6   /* Modulation mode select bit */
1319
#define     inv07       invc0_addr.bit.b7   /* Software trigger select bit */
1320

  
1321
/*------------------------------------------------------
1322
    Three-phase PWM control register 1
1323
------------------------------------------------------*/
1324
union byte_def invc1_addr;
1325
#define     invc1       invc1_addr.byte
1326

  
1327
#define     inv10       invc1_addr.bit.b0   /* Timer A1,A2 and A4 start trigger select bit */
1328
#define     inv11       invc1_addr.bit.b1   /* Timer A1-1,A2-1,A4-1 control bit */
1329
#define     inv12       invc1_addr.bit.b2   /* Dead time timer count source select bit */
1330
#define     inv13       invc1_addr.bit.b3   /* Carrier wave detect flag */
1331
#define     inv14       invc1_addr.bit.b4   /* Output polarity control bit */
1332
#define     inv15       invc1_addr.bit.b5   /* Dead time disable bit */
1333
#define     inv16       invc1_addr.bit.b6   /* Dead time timer trigger select bit */
1334
                                            /* (b7) Reserved bit (Set to 0) */
1335

  
1336
/*------------------------------------------------------
1337
    Three-phase output buffer register 0
1338
------------------------------------------------------*/
1339
union byte_def idb0_addr;
1340
#define     idb0        idb0_addr.byte
1341

  
1342
#define     du0         idb0_addr.bit.b0    /*  U-phase output buffer 0 */
1343
#define     dub0        idb0_addr.bit.b1    /* ~U-phase output buffer 0 */
1344
#define     dv0         idb0_addr.bit.b2    /*  V-phase output buffer 0 */
1345
#define     dvb0        idb0_addr.bit.b3    /* ~V-phase output buffer 0 */
1346
#define     dw0         idb0_addr.bit.b4    /*  W-phase output buffer 0 */
1347
#define     dwb0        idb0_addr.bit.b5    /* ~W-phase output buffer 0 */
1348
                                            /* (b7-b6) Reserved bit (Set to 0) */
1349

  
1350
/*------------------------------------------------------
1351
    Three-phase output buffer register 1
1352
------------------------------------------------------*/
1353
union byte_def idb1_addr;
1354
#define     idb1        idb1_addr.byte
1355

  
1356
#define     du1         idb1_addr.bit.b0    /*  U-phase output buffer 1 */
1357
#define     dub1        idb1_addr.bit.b1    /* ~U-phase output buffer 1 */
1358
#define     dv1         idb1_addr.bit.b2    /*  V-phase output buffer 1 */
1359
#define     dvb1        idb1_addr.bit.b3    /* ~V-phase output buffer 1 */
1360
#define     dw1         idb1_addr.bit.b4    /*  W-phase output buffer 1 */
1361
#define     dwb1        idb1_addr.bit.b5    /* ~W-phase output buffer 1 */
1362
                                            /* (b7-b6) Reserved bit (Set to 0) */
1363

  
1364

  
1365
/*------------------------------------------------------
1366
     Dead time timer 
1367
        (1) The MOV instruction should be used to set the DTT register
1368
------------------------------------------------------*/
1369
union byte_def dtt_addr;
1370
#define     dtt     dtt_addr.byte
1371

  
1372
/*------------------------------------------------------
1373
    Timer B2 interrupt generation frequency set counter 
1374
        (1) The MOV instruction should be used to the ICTB2 register
1375
------------------------------------------------------*/
1376
union byte_def ictb2_addr;
1377
#define     ictb2       ictb2_addr.byte     /* (b3-b0) function */
1378
                                            /* (b7-b4) Nothing is assigned */
1379

  
1380
/*------------------------------------------------------
1381
    One-shot start flag
1382
------------------------------------------------------*/
1383
union byte_def onsf_addr;
1384
#define     onsf        onsf_addr.byte
1385

  
1386
#define     ta0os       onsf_addr.bit.b0    /* Timer A0 one-shot start flag */
1387
#define     ta1os       onsf_addr.bit.b1    /* Timer A1 one-shot start flag */
1388
#define     ta2os       onsf_addr.bit.b2    /* Timer A2 one-shot start flag */
1389
#define     ta3os       onsf_addr.bit.b3    /* Timer A3 one-shot start flag */
1390
#define     ta4os       onsf_addr.bit.b4    /* Timer A4 one-shot start flag */
1391
#define     tazie       onsf_addr.bit.b5    /* Z-phase input enable bit */
1392
#define     ta0tgl      onsf_addr.bit.b6    /* Timer A0 event/trigger select bit */
1393
#define     ta0tgh      onsf_addr.bit.b7    /* Timer A0 event/trigger select bit */
1394

  
1395
/*------------------------------------------------------
1396
    Clock prescaler reset flag
1397
------------------------------------------------------*/
1398
union byte_def cpsrf_addr;
1399
#define     cpsrf       cpsrf_addr.byte
1400
                                            /* (b6-b0) Nothing is assigned */
1401
#define     cpsr        cpsrf_addr.bit.b7   /* Clock prescaler reset flag */
1402

  
1403
/*------------------------------------------------------
1404
    Trigger select register
1405
------------------------------------------------------*/
1406
union byte_def trgsr_addr;
1407
#define     trgsr       trgsr_addr.byte
1408

  
1409
#define     ta1tgl      trgsr_addr.bit.b0   /* Timer A1 event/trigger select bit */
1410
#define     ta1tgh      trgsr_addr.bit.b1   /* Timer A1 event/trigger select bit */
1411
#define     ta2tgl      trgsr_addr.bit.b2   /* Timer A2 event/trigger select bit */
1412
#define     ta2tgh      trgsr_addr.bit.b3   /* Timer A2 event/trigger select bit */
1413
#define     ta3tgl      trgsr_addr.bit.b4   /* Timer A3 event/trigger select bit */
1414
#define     ta3tgh      trgsr_addr.bit.b5   /* Timer A3 event/trigger select bit */
1415
#define     ta4tgl      trgsr_addr.bit.b6   /* Timer A4 event/trigger select bit */
1416
#define     ta4tgh      trgsr_addr.bit.b7   /* Timer A4 event/trigger select bit */
1417

  
1418
/*------------------------------------------------------
1419
    Up Down Flag
1420
        (1) The MOV instruction should be used to set the UDF register
1421
------------------------------------------------------*/
1422
union byte_def   udf_addr;               /* Up/down flag */
1423
#define     udf     udf_addr.byte
1424

  
1425
#define     ta0ud   udf_addr.bit.b0     /* Timer A0 up/down flag */
1426
#define     ta1ud   udf_addr.bit.b1     /* Timer A1 up/down flag */
1427
#define     ta2ud   udf_addr.bit.b2     /* Timer A2 up/down flag */
1428
#define     ta3ud   udf_addr.bit.b3     /* Timer A3 up/down flag */
1429
#define     ta4ud   udf_addr.bit.b4     /* Timer A4 up/down flag */
1430
#define     ta2p    udf_addr.bit.b5     /* Timer A2 2-phase pulse signal processing function select bit */
1431
#define     ta3p    udf_addr.bit.b6     /* Timer A3 2-phase pulse signal processing function select bit */
1432
#define     ta4p    udf_addr.bit.b7     /* Timer A4 2-phase pulse signal processing function select bit */
1433

  
1434
/*------------------------------------------------------
1435
    UARTi transmit/receive control register 1 (i=0,1,2,3,4)
1436
------------------------------------------------------*/
1437
/*------------------------------------------------------
1438
    u0c1
1439
------------------------------------------------------*/
1440
union byte_def u0c1_addr;
1441
#define     u0c1            u0c1_addr.byte
1442
#define     te_u0c1         u0c1_addr.bit.b0    /* Transmit enable bit */
1443
#define     ti_u0c1         u0c1_addr.bit.b1    /* Transmit buffer empty flag */
1444
#define     re_u0c1         u0c1_addr.bit.b2    /* Receive enable bit */
1445
#define     ri_u0c1         u0c1_addr.bit.b3    /* Receive complete flag */
1446
#define     u0irs_u0c1      u0c1_addr.bit.b4    /* UARTi transmit interrupt cause select bit */
1447
#define     u0rrm_u0c1      u0c1_addr.bit.b5    /* UARTi continuous receive mode enable bit */
1448
#define     u0lch_u0c1      u0c1_addr.bit.b6    /* Data logic select bit */
1449
#define     sclkstpb_u0c1   u0c1_addr.bit.b7    /* Clock divide synchronizing stop bit */
1450
#define     u0ere_u0c1      u0c1_addr.bit.b7    /* Error signal output enable bit */
1451

  
1452
/*------------------------------------------------------
1453
    u1c1
1454
------------------------------------------------------*/
1455
union byte_def u1c1_addr;
1456
#define     u1c1            u1c1_addr.byte
1457
#define     te_u1c1         u1c1_addr.bit.b0
1458
#define     ti_u1c1         u1c1_addr.bit.b1
1459
#define     re_u1c1         u1c1_addr.bit.b2
1460
#define     ri_u1c1         u1c1_addr.bit.b3
1461
#define     u1irs_u1c1      u1c1_addr.bit.b4
1462
#define     u1rrm_u1c1      u1c1_addr.bit.b5
1463
#define     u1lch_u1c1      u1c1_addr.bit.b6
1464
#define     sclkstpb_u1c1   u1c1_addr.bit.b7
1465
#define     u1ere_u1c1      u1c1_addr.bit.b7
1466

  
1467
/*------------------------------------------------------
1468
    u2c1
1469
------------------------------------------------------*/
1470
union byte_def u2c1_addr;
1471
#define     u2c1            u2c1_addr.byte
1472
#define     te_u2c1         u2c1_addr.bit.b0
1473
#define     ti_u2c1         u2c1_addr.bit.b1
1474
#define     re_u2c1         u2c1_addr.bit.b2
1475
#define     ri_u2c1         u2c1_addr.bit.b3
1476
#define     u2irs_u2c1      u2c1_addr.bit.b4
1477
#define     u2rrm_u2c1      u2c1_addr.bit.b5
1478
#define     u2lch_u2c1      u2c1_addr.bit.b6
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