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1 2 jalaffon
/************************************************************************************
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*                                                                                   *
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*   File name : sfr32c87.h                                                          *
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*   Contents  : Definition of M32C/87 Group SFR                                     *
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*                                                                                   *
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*   Copyright, 2003 RENESAS TECHNOLOGY CORPORATION                                  *
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*                   AND RENESAS SOLUTIONS CORPORATION                               *
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*                                                                                   *
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*   Note      :                                                                     *
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*                                                                                   *
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*   Version   : Ver 0.01 (04-09-23) Preliminary                                     *
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*                       These data made based on M32C/85 Group H/W Manual Rev.0.30  *
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*   Version   : Ver 0.02 (04-12-02) Preliminary                                     *
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*   Version   : Ver 0.03 (04-12-22) Preliminary                                     *
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*   Version   : Ver 0.04 (05-12-08) Preliminary                                     *
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*   Version   : Ver 0.05 (06-01-23) Preliminary                                     *
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*                                                                                   *
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*************************************************************************************/
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/*
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  note:
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    This data is a freeware that SFR for M32C/87 group are described.
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    RENESAS TECHNOLOGY CORPORATION and RENESAS SOLUTIONS CORPORATION assume
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    no responsibility for any damage that occurred by this data.
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*/
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/************************************************************************
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*   declare SFR address                                                 *
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************************************************************************/
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#pragma ADDRESS     pm0_addr    0004H       /* Processor mode register 0 */
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#pragma ADDRESS     pm1_addr    0005H       /* Processor mode register 1 */
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#pragma ADDRESS     cm0_addr    0006H       /* System clock control register 0 */
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#pragma ADDRESS     cm1_addr    0007H       /* System clock control register 1 */
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#pragma ADDRESS     aier_addr   0009H       /* Address match interrupt enable register */
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#pragma ADDRESS     prcr_addr   000aH       /* Protect register */
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#pragma ADDRESS     ds_addr     000bH       /* External data bus width control register */
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#pragma ADDRESS     mcd_addr    000cH       /* Main clock division register */
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#pragma ADDRESS     cm2_addr    000dH       /* Oscillation stop detect register */
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#pragma ADDRESS     wdts_addr   000eH       /* Watchdog timer start register */
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#pragma ADDRESS     wdc_addr    000fH       /* Watchdog timer control register */
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#pragma ADDRESS     rmad0_addr  0010H       /* Address match interrupt register 0 */
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#pragma ADDRESS     pm2_addr    0013H       /* Processor mode register 2 */
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#pragma ADDRESS     rmad1_addr  0014H       /* Address match interrupt register 1 */
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#pragma ADDRESS     vcr2_addr   0017H       /* Voltage detection register 2 */
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#pragma ADDRESS     rmad2_addr  0018H       /* Address match interrupt register 2 */
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#pragma ADDRESS     vcr1_addr   001bH       /* Voltage detection register 1 */
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#pragma ADDRESS     rmad3_addr  001cH       /* Address match interrupt register 3 */
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#pragma ADDRESS     plc_addr    0026H       /* PLL control register */
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#pragma ADDRESS     plc0_addr   0026H       /* PLL control register 0 */
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#pragma ADDRESS     plc1_addr   0027H       /* PLL control register 1 */
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#pragma ADDRESS     rmad4_addr  0028H       /* Address match interrupt register 4 */
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#pragma ADDRESS     rmad5_addr  002CH       /* Address match interrupt register 5 */
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#pragma ADDRESS     d4int_addr  002FH       /* Voltage down detect interrupt register */
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#pragma ADDRESS     rmad6_addr  0038H       /* Address match interrupt register 6 */
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#pragma ADDRESS     rmad7_addr  003CH       /* Address match interrupt register 7 */
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#pragma ADDRESS     ewcr0_addr  0048H       /* External space wait control register 0 */
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#pragma ADDRESS     ewcr1_addr  0049H       /* External space wait control register 1 */
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#pragma ADDRESS     ewcr2_addr  004AH       /* External space wait control register 2 */
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#pragma ADDRESS     ewcr3_addr  004BH       /* External space wait control register 3 */
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#pragma ADDRESS     fmr1_addr   0055H       /* Flash Memory Control Register 1 */
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#pragma ADDRESS     fmr_addr    0057H       /* Flash memory control register 0 */
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#pragma ADDRESS     fmr0_addr   0057H       /* Flash memory control register 0 */
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#pragma ADDRESS     dm0ic_addr  0068H       /* DMA0 interrupt control register */
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#pragma ADDRESS     tb5ic_addr  0069H       /* Timer B5 interrupt register */
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#pragma ADDRESS     dm2ic_addr  006aH       /* DMA2 interrupt register */
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#pragma ADDRESS     s2ric_addr  006bH       /* UART2 receive/ack interrupt control register */
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#pragma ADDRESS     ta0ic_addr  006cH       /* Timer A0 interrupt control register */
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#pragma ADDRESS     s3ric_addr  006dH       /* UART3 receive/ack interrupt control register */
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#pragma ADDRESS     ta2ic_addr  006eH       /* Timer A2 interrupt control register */
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#pragma ADDRESS     s4ric_addr  006fH       /* UART4 receive/ack interrupt control register */
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#pragma ADDRESS     ta4ic_addr  0070H       /* Timer A4 interrupt control register */
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#pragma ADDRESS     bcn0ic_addr 0071H       /* Bus collision (UART0) interrupt control register */
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#pragma ADDRESS     bcn3ic_addr 0071H       /* Bus collision (UART3) interrupt control register */
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#pragma ADDRESS     s0ric_addr  0072H       /* UART0 receive interrupt control register */
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#pragma ADDRESS     ad0ic_addr  0073H       /* A/D0 conversion interrupt control register */
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#pragma ADDRESS     s1ric_addr  0074H       /* UART1 receive interrupt control register */
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#pragma ADDRESS     iio0ic_addr 0075H       /* Intelligent I/O interrupt control register 0 */
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#pragma ADDRESS     can3ic_addr 0075H       /* CAN interrupt 3 control register */
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#pragma ADDRESS     tb1ic_addr  0076H       /* Timer B1 interrupt control register */
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#pragma ADDRESS     iio2ic_addr 0077H       /* Intelligent I/O interrupt control register 2 */
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#pragma ADDRESS     tb3ic_addr  0078H       /* Timer B3 interrupt control register */
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#pragma ADDRESS     iio4ic_addr 0079H       /* Intelligent I/O interrupt control register 4 */
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#pragma ADDRESS     int5ic_addr 007aH       /* INT5~ interrupt control register */
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#pragma ADDRESS     iio6ic_addr 007bH       /* Intelligent I/O interrupt control register 6 */
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#pragma ADDRESS     int3ic_addr 007cH       /* INT3~ interrupt control register */
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#pragma ADDRESS     iio8ic_addr 007dH       /* Intelligent I/O interrupt control register 8 */
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#pragma ADDRESS     int1ic_addr 007eH       /* INT1~ interrupt control register */
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#pragma ADDRESS     iio10ic_addr 007fH      /* Intelligent I/O interrupt control register 10 */
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#pragma ADDRESS     can1ic_addr 007fH       /* CAN Interrupt 1 Control Register */
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#pragma ADDRESS     iio11ic_addr 0081H      /* Intelligent I/O interrupt control register 11 */
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#pragma ADDRESS     can2ic_addr 0081H       /* CAN Interrupt 2 Control Register */
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#pragma ADDRESS     dm1ic_addr  0088H       /* DMA1 interrupt control register */
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#pragma ADDRESS     s2tic_addr  0089H       /* UART2 transmit/nack interrupt control register */
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#pragma ADDRESS     dm3ic_addr  008aH       /* DMA3 interrupt control register */
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#pragma ADDRESS     s3tic_addr  008bH       /* UART3 transmit/nack interrupt control register */
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#pragma ADDRESS     ta1ic_addr  008cH       /* Timer A1 interrupt control register */
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#pragma ADDRESS     s4tic_addr  008dH       /* UART4 transmit/nack interrupt control register */
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#pragma ADDRESS     ta3ic_addr  008eH       /* Timer A3 interrupt control register */
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#pragma ADDRESS     bcn2ic_addr 008fH       /* Bus collision (UART2) interrupt control register */
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#pragma ADDRESS     s0tic_addr  0090H       /* UART0 transmit interrupt control register */
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#pragma ADDRESS     bcn1ic_addr 0091H       /* Bus collision (UART1) interrupt control register*/
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#pragma ADDRESS     bcn4ic_addr 0091H       /* Bus collision (UART4) interrupt control register */
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#pragma ADDRESS     s1tic_addr  0092H       /* UART1 transmit interrupt control register */
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#pragma ADDRESS     kupic_addr  0093H       /* Key input interrupt control register */
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#pragma ADDRESS     tb0ic_addr  0094H       /* Timer B0 interrupt control register */
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#pragma ADDRESS     iio1ic_addr 0095H       /* Intelligent I/O interrupt control register 1 */
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#pragma ADDRESS     can4ic_addr 0095H       /* CAN Interrupt 4 Control Register */
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#pragma ADDRESS     tb2ic_addr  0096H       /* Timer B2 interrupt control register */
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#pragma ADDRESS     iio3ic_addr 0097H       /* Intelligent I/O interrupt control register 3 */
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#pragma ADDRESS     tb4ic_addr  0098H       /* Timer B4 interrupt control register */
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#pragma ADDRESS     iio5ic_addr 0099H       /* Intelligent I/O interrupt control register 5 */
127
#pragma ADDRESS     can5ic_addr 0099H       /* CAN Interrupt 5 Control Register */
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#pragma ADDRESS     int4ic_addr 009aH       /* INT4~ interrupt control register */
129
#pragma ADDRESS     iio7ic_addr 009bH       /* Intelligent I/O interrupt control register 7 */
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#pragma ADDRESS     int2ic_addr 009cH       /* INT2~ interrupt control register */
131
#pragma ADDRESS     iio9ic_addr 009dH       /* Intelligent I/O interrupt control register 9 */
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#pragma ADDRESS     can0ic_addr 009dH       /* CAN0 Interrupt Control Register*/
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#pragma ADDRESS     int0ic_addr 009eH       /* INT0~ interrupt control register */
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#pragma ADDRESS     rlvl_addr   009fH       /* Exit priority register */
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#pragma ADDRESS     iio0ir_addr 00a0H       /* Interrupt request register 0 */
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#pragma ADDRESS     iio1ir_addr 00a1H       /* Interrupt request register 1 */
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#pragma ADDRESS     iio2ir_addr 00a2H       /* Interrupt request register 2 */
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#pragma ADDRESS     iio3ir_addr 00a3H       /* Interrupt request register 3 */
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#pragma ADDRESS     iio4ir_addr 00a4H       /* Interrupt request register 4 */
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#pragma ADDRESS     iio5ir_addr 00a5H       /* Interrupt request register 5 */
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#pragma ADDRESS     iio6ir_addr 00a6H       /* Interrupt request register 6 */
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#pragma ADDRESS     iio7ir_addr 00a7H       /* Interrupt request register 7 */
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#pragma ADDRESS     iio8ir_addr 00a8H       /* Interrupt request register 8 */
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#pragma ADDRESS     iio9ir_addr 00a9H       /* Interrupt request register 9 */
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#pragma ADDRESS     iio10ir_addr 00aaH      /* Interrupt request register 10 */
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#pragma ADDRESS     iio11ir_addr 00abH      /* Interrupt request register 11 */
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#pragma ADDRESS     iio0ie_addr 00b0H       /* Interrupt enable register 0 */
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#pragma ADDRESS     iio1ie_addr 00b1H       /* Interrupt enable register 1 */
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#pragma ADDRESS     iio2ie_addr 00b2H       /* Interrupt enable register 2 */
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#pragma ADDRESS     iio3ie_addr 00b3H       /* Interrupt enable register 3 */
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#pragma ADDRESS     iio4ie_addr 00b4H       /* Interrupt enable register 4 */
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#pragma ADDRESS     iio5ie_addr 00b5H       /* Interrupt enable register 5 */
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#pragma ADDRESS     iio6ie_addr 00b6H       /* Interrupt enable register 6 */
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#pragma ADDRESS     iio7ie_addr 00b7H       /* Interrupt enable register 7 */
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#pragma ADDRESS     iio8ie_addr 00b8H       /* Interrupt enable register 8 */
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#pragma ADDRESS     iio9ie_addr 00b9H       /* Interrupt enable register 9 */
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#pragma ADDRESS     iio10ie_addr 00baH      /* Interrupt enable register 10 */
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#pragma ADDRESS     iio11ie_addr 00bbH      /* Interrupt enable register 11 */
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#pragma ADDRESS     g0rb_addr   00e8H       /* SI/O receive buffer register 0 */
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#pragma ADDRESS     g0tb_addr   00eaH       /* Transmit buffer register 0 */
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#pragma ADDRESS     g0dr_addr   00eaH       /* Receive data register 0 */
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#pragma ADDRESS     g0ri_addr   00ecH       /* Receive input register 0 */
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#pragma ADDRESS     g0mr_addr   00edH       /* SI/O communication control register 0 */
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#pragma ADDRESS     g0to_addr   00eeH       /* Transmit output register 0 */
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#pragma ADDRESS     g0cr_addr   00efH       /* SI/O communication control register 0 */
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#pragma ADDRESS     g0cmp0_addr 00f0H       /* Data compare register 00 */
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#pragma ADDRESS     g0cmp1_addr 00f1H       /* Data compare register 01 */
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#pragma ADDRESS     g0cmp2_addr 00f2H       /* Data compare register 02 */
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#pragma ADDRESS     g0cmp3_addr 00f3H       /* Data compare register 03 */
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#pragma ADDRESS     g0msk0_addr 00f4H       /* Data mask register 00 */
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#pragma ADDRESS     g0msk1_addr 00f5H       /* Data mask register 01 */
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#pragma ADDRESS     ccs_addr    00f6H       /* Communication clock select register */
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#pragma ADDRESS     g0rcrc_addr 00f8H       /* Receive CRC code register 0 */
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#pragma ADDRESS     g0tcrc_addr 00faH       /* Transmit CRC code register 0 */
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#pragma ADDRESS     g0emr_addr  00fcH       /* SI/O expansion mode register 0 */
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#pragma ADDRESS     g0erc_addr  00fdH       /* SI/O expansion receive control register 0 */
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#pragma ADDRESS     g0irf_addr  00feH       /* SI/O special communication interrupt detect register 0 */
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#pragma ADDRESS     g0etc_addr  00ffH       /* SI/O expansion transmit control register 0 */
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#pragma ADDRESS     g1tm0_addr  0100H       /* Time measurement register 10 */
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#pragma ADDRESS     g1po0_addr  0100H       /* Waveform generate register 10 */
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#pragma ADDRESS     g1tm1_addr  0102H       /* Time measurement register 11 */
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#pragma ADDRESS     g1po1_addr  0102H       /* Waveform generate register 11 */
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#pragma ADDRESS     g1tm2_addr  0104H       /* Time measurement register 12 */
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#pragma ADDRESS     g1po2_addr  0104H       /* Waveform generate register 12 */
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#pragma ADDRESS     g1tm3_addr  0106H       /* Time measurement register 13 */
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#pragma ADDRESS     g1po3_addr  0106H       /* Waveform generate register 13 */
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#pragma ADDRESS     g1tm4_addr  0108H       /* Time measurement register 14 */
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#pragma ADDRESS     g1po4_addr  0108H       /* Waveform generate register 14 */
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#pragma ADDRESS     g1tm5_addr  010aH       /* Time measurement register 15 */
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#pragma ADDRESS     g1po5_addr  010aH       /* Waveform generate register 15 */
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#pragma ADDRESS     g1tm6_addr  010cH       /* Time measurement register 16 */
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#pragma ADDRESS     g1po6_addr  010cH       /* Waveform generate register 16 */
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#pragma ADDRESS     g1tm7_addr  010eH       /* Time measurement register 17 */
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#pragma ADDRESS     g1po7_addr  010eH       /* Waveform generate register 17 */
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#pragma ADDRESS     g1pocr0_addr 0110H      /* Waveform generate control register 10 */
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#pragma ADDRESS     g1pocr1_addr 0111H      /* Waveform generate control register 11 */
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#pragma ADDRESS     g1pocr2_addr 0112H      /* Waveform generate control register 12 */
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#pragma ADDRESS     g1pocr3_addr 0113H      /* Waveform generate control register 13 */
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#pragma ADDRESS     g1pocr4_addr 0114H      /* Waveform generate control register 14 */
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#pragma ADDRESS     g1pocr5_addr 0115H      /* Waveform generate control register 15 */
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#pragma ADDRESS     g1pocr6_addr 0116H      /* Waveform generate control register 16 */
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#pragma ADDRESS     g1pocr7_addr 0117H      /* Waveform generate control register 17 */
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#pragma ADDRESS     g1tmcr0_addr 0118H      /* Time measurement control register 10 */
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#pragma ADDRESS     g1tmcr1_addr 0119H      /* Time measurement control register 11 */
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#pragma ADDRESS     g1tmcr2_addr 011aH      /* Time measurement control register 12 */
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#pragma ADDRESS     g1tmcr3_addr 011bH      /* Time measurement control register 13 */
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#pragma ADDRESS     g1tmcr4_addr 011cH      /* Time measurement control register 14 */
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#pragma ADDRESS     g1tmcr5_addr 011dH      /* Time measurement control register 15 */
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#pragma ADDRESS     g1tmcr6_addr 011eH      /* Time measurement control register 16 */
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#pragma ADDRESS     g1tmcr7_addr 011fH      /* Time measurement control register 17 */
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#pragma ADDRESS     g1bt_addr    0120H      /* Base timer register 1 */
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#pragma ADDRESS     g1bcr0_addr  0122H      /* Base timer control register 10 */
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#pragma ADDRESS     g1bcr1_addr  0123H      /* Base timer control register 11 */
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#pragma ADDRESS     g1tpr6_addr  0124H      /* Time measurement prescaler register 16 */
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#pragma ADDRESS     g1tpr7_addr  0125H      /* Time measurement prescaler register 17 */
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#pragma ADDRESS     g1fe_addr    0126H      /* Function enable register 1 */
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#pragma ADDRESS     g1fs_addr    0127H      /* Function select register 1 */
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#pragma ADDRESS     g1rb_addr    0128H      /* SI/O receive buffer register 1 */
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#pragma ADDRESS     g1tb_addr    012aH      /* Transmit buffer register 1 */
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#pragma ADDRESS     g1dr_addr    012aH      /* Receive data register 1 */
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#pragma ADDRESS     g1ri_addr    012cH      /* Receive input register 1 */
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#pragma ADDRESS     g1mr_addr    012dH      /* SI/O communication mode register 1 */
230
#pragma ADDRESS     g1to_addr    012eH      /* Transmit output register 1 */
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#pragma ADDRESS     g1cr_addr    012fH      /* SI/O communication control register 1 */
232
#pragma ADDRESS     g1cmp0_addr  0130H      /* Data compare register 10 */
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#pragma ADDRESS     g1cmp1_addr  0131H      /* Data compare register 11 */
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#pragma ADDRESS     g1cmp2_addr  0132H      /* Data compare register 12 */
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#pragma ADDRESS     g1cmp3_addr  0133H      /* Data compare register 13 */
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#pragma ADDRESS     g1msk0_addr  0134H      /* Data mask register 10 */
237
#pragma ADDRESS     g1msk1_addr  0135H      /* Data mask register 11 */
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#pragma ADDRESS     g1rcrc_addr  0138H      /* Receive CRC code register 1 */
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#pragma ADDRESS     g1tcrc_addr  013aH      /* Transmit CRC code register 1 */
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#pragma ADDRESS     g1emr_addr   013cH      /* SI/O extended mode register 1 */
243
#pragma ADDRESS     g1erc_addr   013dH      /* SI/O extended receive control register 1 */
244
#pragma ADDRESS     g1irf_addr   013eH      /* SI/O special communication interrupt detect register 1 */
245
#pragma ADDRESS     g1etc_addr   013fH      /* SI/O extended transmit control register 1 */
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#pragma ADDRESS     g2po0_addr   0140H
248
#pragma ADDRESS     g2po1_addr   0142H
249
#pragma ADDRESS     g2po2_addr   0144H
250
#pragma ADDRESS     g2po3_addr   0146H
251
#pragma ADDRESS     g2po4_addr   0148H
252
#pragma ADDRESS     g2po5_addr   014aH
253
#pragma ADDRESS     g2po6_addr   014cH
254
#pragma ADDRESS     g2po7_addr   014eH
255
#pragma ADDRESS     g2pocr0_addr 0150H
256
#pragma ADDRESS     g2pocr1_addr 0151H
257
#pragma ADDRESS     g2pocr2_addr 0152H
258
#pragma ADDRESS     g2pocr3_addr 0153H
259
#pragma ADDRESS     g2pocr4_addr 0154H
260
#pragma ADDRESS     g2pocr5_addr 0155H
261
#pragma ADDRESS     g2pocr6_addr 0156H
262
#pragma ADDRESS     g2pocr7_addr 0157H
263
264
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#pragma ADDRESS     g2bt_addr    0160H
266
#pragma ADDRESS     g2bcr0_addr  0162H
267
#pragma ADDRESS     g2bcr1_addr  0163H
268
#pragma ADDRESS     btsr_addr    0164H
269
270
#pragma ADDRESS     g2fe_addr    0166H
271
#pragma ADDRESS     g2rtp_addr   0167H
272
273
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#pragma ADDRESS     g2mr_addr    016aH
275
#pragma ADDRESS     g2cr_addr    016bH
276
#pragma ADDRESS     g2tb_addr    016cH
277
#pragma ADDRESS     g2rb_addr    016eH
278
#pragma ADDRESS     iear_addr    0170H
279
#pragma ADDRESS     iecr_addr    0172H
280
#pragma ADDRESS     ietif_addr   0173H
281
#pragma ADDRESS     ierif_addr   0174H
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#pragma ADDRESS     ipsb_addr    0177H      /* Input function select register B */
285
#pragma ADDRESS     ips_addr     0178H      /* Input function select register */
286
#pragma ADDRESS     ipsa_addr    0179H      /* Input function select register A */
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288
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#pragma ADDRESS     u5mr_addr   01c0H       /* UART5 transmit/receive mode register */
290
#pragma ADDRESS     u5brg_addr  01c1H       /* UART5 bit rate generator */
291
#pragma ADDRESS     u5tb_addr   01c2H       /* UART5 transmit buffer register */
292
#pragma ADDRESS     u5c0_addr   01c4H       /* UART5 transmit/receive control register 0 */
293
#pragma ADDRESS     u5c1_addr   01c5H       /* UART5 transmit/receive control register 1 */
294
#pragma ADDRESS     u5rb_addr   01c6H       /* UART5 receive buffer register */
295
#pragma ADDRESS     u6mr_addr   01c8H       /* UART6 transmit/receive mode register */
296
#pragma ADDRESS     u6brg_addr  01c9H       /* UART6 bit rate generator */
297
#pragma ADDRESS     u6tb_addr   01caH       /* UART6 transmit buffer register */
298
#pragma ADDRESS     u6c0_addr   01ccH       /* UART6 transmit/receive control register 0 */
299
#pragma ADDRESS     u6c1_addr   01cdH       /* UART6 transmit/receive control register 1 */
300
#pragma ADDRESS     u6rb_addr   01ceH       /* UART6 receive buffer register */
301
#pragma ADDRESS     u56con_addr 01d0H
302
#pragma ADDRESS     u56is_addr  01d1H
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#pragma ADDRESS     rtp0r_addr  01d8H
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#pragma ADDRESS     rtp1r_addr  01d9H
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#pragma ADDRESS     rtp2r_addr  01daH
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#pragma ADDRESS     rtp3r_addr  01dbH
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/************************************************************************
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*   CAN 0 SFR Address area                                              *
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************************************************************************/
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#pragma ADDRESS     c0slot          01e0H      /* CAN0 Message Slot Buffer */
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#pragma ADDRESS     c0slot0         01e0H      /* CAN0 Message Slot Buffer 0 */
317
#pragma ADDRESS     c0slot1         01f0H      /* CAN0 Message Slot Buffer 1 */
318
#pragma ADDRESS     c0ctlr0_addr    0200H      /* CAN0 Control Register 0 */
319
#pragma ADDRESS     c0str_addr      0202H      /* CAN0 Status Register */
320
#pragma ADDRESS     c0idr_addr      0204H      /* CAN0 Extended ID Register */
321
#pragma ADDRESS     c0conr_addr     0206H      /* CAN0 Configuration Register */
322
#pragma ADDRESS     c0tsr_addr      0208H      /* CAN0 Time Stamp Register */
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#pragma ADDRESS     c0tec_addr      020aH      /* CAN0 Transmit Error Counter */
324
#pragma ADDRESS     c0rec_addr      020bH      /* CAN0 Receive Error Counter */
325
#pragma ADDRESS     c0sistr_addr    020cH      /* CAN0 Slot Interrupt Status Register */
326
#pragma ADDRESS     c0simkr_addr    0210H      /* CAN0 Slot Interrupt Mask Register */
327
#pragma ADDRESS     c0eimkr_addr    0214H      /* CAN0 Error Interrupt Mask Register */
328
#pragma ADDRESS     c0eistr_addr    0215H      /* CAN0 Error Interrupt Status Register */
329
#pragma ADDRESS     c0efr_addr      0216H      /* CAN0 Error Factor Register  */
330
#pragma ADDRESS     c0brp_addr      0217H      /* CAN0 Baud Rate Prescaler */
331
#pragma ADDRESS     c0mdr_addr      0219H      /* CAN0 Mode Register */
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#pragma ADDRESS     c0ssctlr_addr   0220H      /* (BANK0) CAN0 Single Shot Control Register */
333
#pragma ADDRESS     c0ssstr_addr    0224H      /* (BANK0) CAN0 Single Shot Status Register */
334
#pragma ADDRESS     c0mctl          0230H      /* (BANK0) CAN0 Message Control Register */
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#pragma ADDRESS     c0mctl0         0230H      /* (BANK0) CAN0 Message Slot0 Control Register */
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#pragma ADDRESS     c0mctl1         0231H      /* (BANK0) CAN0 Message Slot1 Control Register */
337
#pragma ADDRESS     c0mctl2         0232H      /* (BANK0) CAN0 Message Slot2 Control Register */
338
#pragma ADDRESS     c0mctl3         0233H      /* (BANK0) CAN0 Message Slot3 Control Register */
339
#pragma ADDRESS     c0mctl4         0234H      /* (BANK0) CAN0 Message Slot4 Control Register */
340
#pragma ADDRESS     c0mctl5         0235H      /* (BANK0) CAN0 Message Slot5 Control Register */
341
#pragma ADDRESS     c0mctl6         0236H      /* (BANK0) CAN0 Message Slot6 Control Register */
342
#pragma ADDRESS     c0mctl7         0237H      /* (BANK0) CAN0 Message Slot7 Control Register */
343
#pragma ADDRESS     c0mctl8         0238H      /* (BANK0) CAN0 Message Slot8 Control Register */
344
#pragma ADDRESS     c0mctl9         0239H      /* (BANK0) CAN0 Message Slot9 Control Register */
345
#pragma ADDRESS     c0mctl10        023aH      /* (BANK0) CAN0 Message Slot10 Control Register */
346
#pragma ADDRESS     c0mctl11        023bH      /* (BANK0) CAN0 Message Slot11 Control Register */
347
#pragma ADDRESS     c0mctl12        023cH      /* (BANK0) CAN0 Message Slot12 Control Register */
348
#pragma ADDRESS     c0mctl13        023dH      /* (BANK0) CAN0 Message Slot13 Control Register */
349
#pragma ADDRESS     c0mctl14        023eH      /* (BANK0) CAN0 Message Slot14 Control Register */
350
#pragma ADDRESS     c0mctl15        023fH      /* (BANK0) CAN0 Message Slot15 Control Register */
351
#pragma ADDRESS     c0gmr           0228H      /* (BANK1) CAN0 Global Mask Register */
352
#pragma ADDRESS     c0gmr0_addr     0228H      /* (BANK1) CAN0 Global Mask Register 0 */
353
#pragma ADDRESS     c0gmr1_addr     0229H      /* (BANK1) CAN0 Global Mask Register 1 */
354
#pragma ADDRESS     c0gmr2_addr     022aH      /* (BANK1) CAN0 Global Mask Register 2 */
355
#pragma ADDRESS     c0gmr3_addr     022bH      /* (BANK1) CAN0 Global Mask Register 3 */
356
#pragma ADDRESS     c0gmr4_addr     022cH      /* (BANK1) CAN0 Global Mask Register 4 */
357
#pragma ADDRESS     c0lmar          0230H      /* (BANK1) CAN0 Local Mask A Register */
358
#pragma ADDRESS     c0lmar0_addr    0230H      /* (BANK1) CAN0 Local Mask A Register 0 */
359
#pragma ADDRESS     c0lmar1_addr    0231H      /* (BANK1) CAN0 Local Mask A Register 1 */
360
#pragma ADDRESS     c0lmar2_addr    0232H      /* (BANK1) CAN0 Local Mask A Register 2 */
361
#pragma ADDRESS     c0lmar3_addr    0233H      /* (BANK1) CAN0 Local Mask A Register 3 */
362
#pragma ADDRESS     c0lmar4_addr    0234H      /* (BANK1) CAN0 Local Mask A Register 4 */
363
#pragma ADDRESS     c0lmbr          0238H      /* (BANK1) CAN0 Local Mask B Register */
364
#pragma ADDRESS     c0lmbr0_addr    0238H      /* (BANK1) CAN0 Local Mask B Register 0 */
365
#pragma ADDRESS     c0lmbr1_addr    0239H      /* (BANK1) CAN0 Local Mask B Register 1 */
366
#pragma ADDRESS     c0lmbr2_addr    023aH      /* (BANK1) CAN0 Local Mask B Register 2 */
367
#pragma ADDRESS     c0lmbr3_addr    023bH      /* (BANK1) CAN0 Local Mask B Register 3 */
368
#pragma ADDRESS     c0lmbr4_addr    023cH      /* (BANK1) CAN0 Local Mask B Register 4 */
369
#pragma ADDRESS     c0sbs_addr      0240H      /* CAN0 Slot Buffer Select Register */
370
#pragma ADDRESS     c0ctlr1_addr    0241H      /* CAN0 Control Register 1 */
371
#pragma ADDRESS     c0slpr_addr     0242H      /* CAN0 Sleep Control Register */
372
#pragma ADDRESS     c0afs_addr      0244H      /* CAN0 Acceptance Filter Support Register */
373
374
375
/************************************************************************
376
*   CAN 1 SFR Address area                                              *
377
************************************************************************/
378
#pragma ADDRESS     c1slot          0260H      /* CAN1 Message Slot Buffer */
379
#pragma ADDRESS     c1slot0         0260H      /* CAN1 Message Slot Buffer 0 */
380
#pragma ADDRESS     c1slot1         0270H      /* CAN1 Message Slot Buffer 1 */
381
#pragma ADDRESS     c1ctlr0_addr    0280H      /* CAN1 Control Register 0 */
382
#pragma ADDRESS     c1str_addr      0282H      /* CAN1 Status Register */
383
#pragma ADDRESS     c1idr_addr      0284H      /* CAN1 Extended ID Register */
384
#pragma ADDRESS     c1conr_addr     0286H      /* CAN1 Configuration Register */
385
#pragma ADDRESS     c1tsr_addr      0288H      /* CAN1 Time Stamp Register */
386
#pragma ADDRESS     c1tec_addr      028aH      /* CAN1 Transmit Error Counter */
387
#pragma ADDRESS     c1rec_addr      028bH      /* CAN1 Receive Error Counter */
388
#pragma ADDRESS     c1sistr_addr    028cH      /* CAN1 Slot Interrupt Status Register */
389
#pragma ADDRESS     c1simkr_addr    0290H      /* CAN1 Slot Interrupt Mask Register */
390
#pragma ADDRESS     c1eimkr_addr    0294H      /* CAN1 Error Interrupt Mask Register */
391
#pragma ADDRESS     c1eistr_addr    0295H      /* CAN1 Error Interrupt Status Register */
392
#pragma ADDRESS     c1efr_addr      0296H      /* CAN1 Error Factor Register  */
393
#pragma ADDRESS     c1brp_addr      0297H      /* CAN1 Baud Rate Prescaler */
394
#pragma ADDRESS     c1mdr_addr      0299H      /* CAN1 Mode Register */
395
#pragma ADDRESS     c1ssctlr_addr   02A0H      /* (BANK0) CAN1 Single Shot Control Register */
396
#pragma ADDRESS     c1ssstr_addr    02A4H      /* (BANK0) CAN1 Single Shot Status Register */
397
#pragma ADDRESS     c1mctl          02B0H      /* (BANK0) CAN1 Message Control Register */
398
#pragma ADDRESS     c1mctl0         02B0H      /* (BANK0) CAN1 Message Slot0 Control Register */
399
#pragma ADDRESS     c1mctl1         02B1H      /* (BANK0) CAN1 Message Slot1 Control Register */
400
#pragma ADDRESS     c1mctl2         02B2H      /* (BANK0) CAN1 Message Slot2 Control Register */
401
#pragma ADDRESS     c1mctl3         02B3H      /* (BANK0) CAN1 Message Slot3 Control Register */
402
#pragma ADDRESS     c1mctl4         02B4H      /* (BANK0) CAN1 Message Slot4 Control Register */
403
#pragma ADDRESS     c1mctl5         02B5H      /* (BANK0) CAN1 Message Slot5 Control Register */
404
#pragma ADDRESS     c1mctl6         02B6H      /* (BANK0) CAN1 Message Slot6 Control Register */
405
#pragma ADDRESS     c1mctl7         02B7H      /* (BANK0) CAN1 Message Slot7 Control Register */
406
#pragma ADDRESS     c1mctl8         02B8H      /* (BANK0) CAN1 Message Slot8 Control Register */
407
#pragma ADDRESS     c1mctl9         02B9H      /* (BANK0) CAN1 Message Slot9 Control Register */
408
#pragma ADDRESS     c1mctl10        02baH      /* (BANK0) CAN1 Message Slot10 Control Register */
409
#pragma ADDRESS     c1mctl11        02bbH      /* (BANK0) CAN1 Message Slot11 Control Register */
410
#pragma ADDRESS     c1mctl12        02bcH      /* (BANK0) CAN1 Message Slot12 Control Register */
411
#pragma ADDRESS     c1mctl13        02bdH      /* (BANK0) CAN1 Message Slot13 Control Register */
412
#pragma ADDRESS     c1mctl14        02beH      /* (BANK0) CAN1 Message Slot14 Control Register */
413
#pragma ADDRESS     c1mctl15        02bfH      /* (BANK0) CAN1 Message Slot15 Control Register */
414
#pragma ADDRESS     c1gmr           02a8H      /* (BANK1) CAN1 Global Mask Register */
415
#pragma ADDRESS     c1gmr0_addr     02a8H      /* (BANK1) CAN1 Global Mask Register 0 */
416
#pragma ADDRESS     c1gmr1_addr     02a9H      /* (BANK1) CAN1 Global Mask Register 1 */
417
#pragma ADDRESS     c1gmr2_addr     02aaH      /* (BANK1) CAN1 Global Mask Register 2 */
418
#pragma ADDRESS     c1gmr3_addr     02abH      /* (BANK1) CAN1 Global Mask Register 3 */
419
#pragma ADDRESS     c1gmr4_addr     02acH      /* (BANK1) CAN1 Global Mask Register 4 */
420
#pragma ADDRESS     c1lmar          02b0H      /* (BANK1) CAN1 Local Mask A Register */
421
#pragma ADDRESS     c1lmar0_addr    02b0H      /* (BANK1) CAN1 Local Mask A Register 0 */
422
#pragma ADDRESS     c1lmar1_addr    02b1H      /* (BANK1) CAN1 Local Mask A Register 1 */
423
#pragma ADDRESS     c1lmar2_addr    02b2H      /* (BANK1) CAN1 Local Mask A Register 2 */
424
#pragma ADDRESS     c1lmar3_addr    02b3H      /* (BANK1) CAN1 Local Mask A Register 3 */
425
#pragma ADDRESS     c1lmar4_addr    02b4H      /* (BANK1) CAN1 Local Mask A Register 4 */
426
#pragma ADDRESS     c1lmbr          02b8H      /* (BANK1) CAN1 Local Mask B Register */
427
#pragma ADDRESS     c1lmbr0_addr    02b8H      /* (BANK1) CAN1 Local Mask B Register 0 */
428
#pragma ADDRESS     c1lmbr1_addr    02b9H      /* (BANK1) CAN1 Local Mask B Register 1 */
429
#pragma ADDRESS     c1lmbr2_addr    02baH      /* (BANK1) CAN1 Local Mask B Register 2 */
430
#pragma ADDRESS     c1lmbr3_addr    02bbH      /* (BANK1) CAN1 Local Mask B Register 3 */
431
#pragma ADDRESS     c1lmbr4_addr    02bcH      /* (BANK1) CAN1 Local Mask B Register 4 */
432
#pragma ADDRESS     c1sbs_addr      0250H      /* CAN1 Slot Buffer Select Register */
433
#pragma ADDRESS     c1ctlr1_addr    0251H      /* CAN1 Control Register 1 */
434
#pragma ADDRESS     c1slpr_addr     0252H      /* CAN1 Sleep Control Register */
435
#pragma ADDRESS     c1afs_addr      0254H      /* CAN1 Acceptance Filter Support Register */
436
437
/************************************************************************
438
*                                                                       *
439
************************************************************************/
440
#pragma ADDRESS     x0r_addr    02c0H       /* X0 register */
441
#pragma ADDRESS     y0r_addr    02c0H       /* Y0 register */
442
#pragma ADDRESS     x1r_addr    02c2H       /* X1 register */
443
#pragma ADDRESS     y1r_addr    02c2H       /* Y1 register */
444
#pragma ADDRESS     x2r_addr    02c4H       /* X2 register */
445
#pragma ADDRESS     y2r_addr    02c4H       /* Y2 register */
446
#pragma ADDRESS     x3r_addr    02c6H       /* X3 register */
447
#pragma ADDRESS     y3r_addr    02c6H       /* Y3 register */
448
#pragma ADDRESS     x4r_addr    02c8H       /* X4 register */
449
#pragma ADDRESS     y4r_addr    02c8H       /* Y4 register */
450
#pragma ADDRESS     x5r_addr    02caH       /* X5 register */
451
#pragma ADDRESS     y5r_addr    02caH       /* Y5 register */
452
#pragma ADDRESS     x6r_addr    02ccH       /* X6 register */
453
#pragma ADDRESS     y6r_addr    02ccH       /* Y6 register */
454
#pragma ADDRESS     x7r_addr    02ceH       /* X7 register */
455
#pragma ADDRESS     y7r_addr    02ceH       /* Y7 register */
456
#pragma ADDRESS     x8r_addr    02d0H       /* X8 register */
457
#pragma ADDRESS     y8r_addr    02d0H       /* Y8 register */
458
#pragma ADDRESS     x9r_addr    02d2H       /* X9 register */
459
#pragma ADDRESS     y9r_addr    02d2H       /* Y9 register */
460
#pragma ADDRESS     x10r_addr   02d4H       /* X10 register */
461
#pragma ADDRESS     y10r_addr   02d4H       /* Y10 register */
462
#pragma ADDRESS     x11r_addr   02d6H       /* X11 register */
463
#pragma ADDRESS     y11r_addr   02d6H       /* Y11 register */
464
#pragma ADDRESS     x12r_addr   02d8H       /* X12 register */
465
#pragma ADDRESS     y12r_addr   02d8H       /* Y12 register */
466
#pragma ADDRESS     x13r_addr   02daH       /* X13 register */
467
#pragma ADDRESS     y13r_addr   02daH       /* Y13 register */
468
#pragma ADDRESS     x14r_addr   02dcH       /* X14 register */
469
#pragma ADDRESS     y14r_addr   02dcH       /* Y14 register */
470
#pragma ADDRESS     x15r_addr   02deH       /* X15 register */
471
#pragma ADDRESS     y15r_addr   02deH       /* Y15 register */
472
#pragma ADDRESS     xyc_addr    02e0H       /* X-Y control register */
473
474
475
#pragma ADDRESS     u1smr4_addr 02e4H       /* UART1 special mode register 4 */
476
#pragma ADDRESS     u1smr3_addr 02e5H       /* UART1 special mode register 3 */
477
#pragma ADDRESS     u1smr2_addr 02e6H       /* UART1 special mode register 2 */
478
#pragma ADDRESS     u1smr_addr  02e7H       /* UART1 special mode register */
479
#pragma ADDRESS     u1mr_addr   02e8H       /* UART1 transmit/receive mode register */
480
#pragma ADDRESS     u1brg_addr  02e9H       /* UART1 bit rate generator */
481
#pragma ADDRESS     u1tb_addr   02eaH       /* UART1 transmit buffer register */
482
#pragma ADDRESS     u1c0_addr   02ecH       /* UART1 transmit/receive control register 0 */
483
#pragma ADDRESS     u1c1_addr   02edH       /* UART1 transmit/receive control register 1 */
484
#pragma ADDRESS     u1rb_addr   02eeH       /* UART1 receive buffer register */
485
486
487
#pragma ADDRESS     u4smr4_addr 02f4H       /* UART4 special mode register 4 */
488
#pragma ADDRESS     u4smr3_addr 02f5H       /* UART4 special mode register 3 */
489
#pragma ADDRESS     u4smr2_addr 02f6H       /* UART4 special mode register 2 */
490
#pragma ADDRESS     u4smr_addr  02f7H       /* UART4 special mode register */
491
#pragma ADDRESS     u4mr_addr   02f8H       /* UART4 transmit/receive mode register */
492
#pragma ADDRESS     u4brg_addr  02f9H       /* UART4 bit rate generator */
493
#pragma ADDRESS     u4tb_addr   02faH       /* UART4 transmit buffer register */
494
#pragma ADDRESS     u4c0_addr   02fcH       /* UART4 transmit/receive control register 0 */
495
#pragma ADDRESS     u4c1_addr   02fdH       /* UART4 transmit/receive control register 1 */
496
#pragma ADDRESS     u4rb_addr   02feH       /* UART4 receive buffer register */
497
498
#pragma ADDRESS     tbsr_addr   0300H       /* Timer B3,4,5 count start flag */
499
500
#pragma ADDRESS     ta11_addr   0302H       /* Timer A1-1 register */
501
#pragma ADDRESS     ta21_addr   0304H       /* Timer A2-1 register */
502
#pragma ADDRESS     ta41_addr   0306H       /* Timer A4-1 register */
503
#pragma ADDRESS     invc0_addr  0308H       /* Three-phase PWM control register 0 */
504
#pragma ADDRESS     invc1_addr  0309H       /* Three-phase PWM control register 1 */
505
#pragma ADDRESS     idb0_addr   030aH       /* Three-phase output buffer register 0 */
506
#pragma ADDRESS     idb1_addr   030bH       /* Three-phase output buffer register 1 */
507
#pragma ADDRESS     dtt_addr    030cH       /* Dead time timer */
508
#pragma ADDRESS     ictb2_addr  030dH       /* Timer B2 interrupt occurences frequency set counter */
509
510
511
#pragma ADDRESS     tb3_addr    0310H       /* Timer B3 register */
512
#pragma ADDRESS     tb4_addr    0312H       /* Timer B4 register */
513
#pragma ADDRESS     tb5_addr    0314H       /* Timer B5 register */
514
515
516
#pragma ADDRESS     tb3mr_addr  031bH       /* Timer B3 mode register */
517
#pragma ADDRESS     tb4mr_addr  031cH       /* Timer B4 mode register */
518
#pragma ADDRESS     tb5mr_addr  031dH       /* Timer B5 mode register */
519
#pragma ADDRESS     ifsra_addr  031eH       /* External interrupt request cause select register 1 */
520
#pragma ADDRESS     ifsr_addr   031fH       /* External interrupt request cause select register */
521
522
523
#pragma ADDRESS     u3smr4_addr 0324H       /* UART3 special mode register 4 */
524
#pragma ADDRESS     u3smr3_addr 0325H       /* UART3 special mode register 3 */
525
#pragma ADDRESS     u3smr2_addr 0326H       /* UART3 special mode register 2 */
526
#pragma ADDRESS     u3smr_addr  0327H       /* UART3 special mode register */
527
#pragma ADDRESS     u3mr_addr   0328H       /* UART3 transmit/receive mode register */
528
#pragma ADDRESS     u3brg_addr  0329H       /* UART3 bit rate generator */
529
#pragma ADDRESS     u3tb_addr   032aH       /* UART3 transmit buffer register */
530
#pragma ADDRESS     u3c0_addr   032cH       /* UART3 transmit/receive control register 0 */
531
#pragma ADDRESS     u3c1_addr   032dH       /* UART3 transmit/receive control register 1 */
532
#pragma ADDRESS     u3rb_addr   032eH       /* UART3 receive buffer register */
533
534
535
#pragma ADDRESS     u2smr4_addr 0334H       /* UART2 special mode register 4 */
536
#pragma ADDRESS     u2smr3_addr 0335H       /* UART2 special mode register 3 */
537
#pragma ADDRESS     u2smr2_addr 0336H       /* UART2 special mode register 2 */
538
#pragma ADDRESS     u2smr_addr  0337H       /* UART2 special mode register */
539
#pragma ADDRESS     u2mr_addr   0338H       /* UART2 transmit/receive mode register */
540
#pragma ADDRESS     u2brg_addr  0339H       /* UART2 bit rate generator */
541
#pragma ADDRESS     u2tb_addr   033aH       /* UART2 transmit buffer register */
542
#pragma ADDRESS     u2c0_addr   033cH       /* UART2 transmit/receive control register 0 */
543
#pragma ADDRESS     u2c1_addr   033dH       /* UART2 transmit/receive control register 1 */
544
#pragma ADDRESS     u2rb_addr   033eH       /* UART2 receive buffer register */
545
#pragma ADDRESS     tabsr_addr  0340H       /* Count start flag */
546
#pragma ADDRESS     cpsrf_addr  0341H       /* Clock prescaler reset flag */
547
#pragma ADDRESS     onsf_addr   0342H       /* One-shot start flag */
548
#pragma ADDRESS     trgsr_addr  0343H       /* Trigger select register */
549
#pragma ADDRESS     udf_addr    0344H       /* Up/down flag */
550
551
#pragma ADDRESS     ta0_addr    0346H       /* Timer A0 register */
552
#pragma ADDRESS     ta1_addr    0348H       /* Timer A1 register */
553
#pragma ADDRESS     ta2_addr    034aH       /* Timer A2 register */
554
#pragma ADDRESS     ta3_addr    034cH       /* Timer A3 register */
555
#pragma ADDRESS     ta4_addr    034eH       /* Timer A4 register */
556
#pragma ADDRESS     tb0_addr    0350H       /* Timer B0 register */
557
#pragma ADDRESS     tb1_addr    0352H       /* Timer B1 register */
558
#pragma ADDRESS     tb2_addr    0354H       /* Timer B2 register */
559
#pragma ADDRESS     ta0mr_addr  0356H       /* Timer A0 mode register */
560
#pragma ADDRESS     ta1mr_addr  0357H       /* Timer A1 mode register */
561
#pragma ADDRESS     ta2mr_addr  0358H       /* Timer A2 mode register */
562
#pragma ADDRESS     ta3mr_addr  0359H       /* Timer A3 mode register */
563
#pragma ADDRESS     ta4mr_addr  035aH       /* Timer A4 mode register */
564
#pragma ADDRESS     tb0mr_addr  035bH       /* Timer B0 mode register */
565
#pragma ADDRESS     tb1mr_addr  035cH       /* Timer B1 mode register */
566
#pragma ADDRESS     tb2mr_addr  035dH       /* Timer B2 mode register */
567
#pragma ADDRESS     tb2sc_addr  035eH       /* Timer B2 special mode register */
568
#pragma ADDRESS     tcspr_addr  035fH       /* Count source prescaler register */
569
570
571
#pragma ADDRESS     u0smr4_addr 0364H       /* UART0 special mode register 4 */
572
#pragma ADDRESS     u0smr3_addr 0365H       /* UART0 special mode register 3 */
573
#pragma ADDRESS     u0smr2_addr 0366H       /* UART0 special mode register 2 */
574
#pragma ADDRESS     u0smr_addr  0367H       /* UART0 special mode register */
575
#pragma ADDRESS     u0mr_addr   0368H       /* UART0 transmit/receive mode register */
576
#pragma ADDRESS     u0brg_addr  0369H       /* UART0 bit rate generator */
577
#pragma ADDRESS     u0tb_addr   036aH       /* UART0 transmit buffer register */
578
#pragma ADDRESS     u0c0_addr   036cH       /* UART0 transmit/receive control register 0 */
579
#pragma ADDRESS     u0c1_addr   036dH       /* UART0 transmit/receive control register 1 */
580
#pragma ADDRESS     u0rb_addr   036eH       /* UART0 receive buffer register */
581
582
583
#pragma ADDRESS     ircon_addr  0372H
584
585
586
#pragma ADDRESS     dm0sl_addr  0378H       /* DMA0 cause select register */
587
#pragma ADDRESS     dm1sl_addr  0379H       /* DMA1 cause select register */
588
#pragma ADDRESS     dm2sl_addr  037aH       /* DMA1 cause select register */
589
#pragma ADDRESS     dm3sl_addr  037bH       /* DMA1 cause select register */
590
#pragma ADDRESS     crcd_addr   037cH       /* CRC data register */
591
#pragma ADDRESS     crcin_addr  037eH       /* CRC input register */
592
593
#pragma ADDRESS     ad00_addr   0380H       /* A/D0 register 0 */
594
#pragma ADDRESS     ad01_addr   0382H       /* A/D0 register 1 */
595
#pragma ADDRESS     ad02_addr   0384H       /* A/D0 register 2 */
596
#pragma ADDRESS     ad03_addr   0386H       /* A/D0 register 3 */
597
#pragma ADDRESS     ad04_addr   0388H       /* A/D0 register 4 */
598
#pragma ADDRESS     ad05_addr   038aH       /* A/D0 register 5 */
599
#pragma ADDRESS     ad06_addr   038cH       /* A/D0 register 6 */
600
#pragma ADDRESS     ad07_addr   038eH       /* A/D0 register 7 */
601
602
603
#pragma ADDRESS     ad0con4_addr 0392H      /* A/D0 control register 4 */
604
605
#pragma ADDRESS     ad0con2_addr 0394H      /* A/D0 control register 2 */
606
#pragma ADDRESS     ad0con3_addr 0395H      /* A/D0 control register 3 */
607
#pragma ADDRESS     ad0con0_addr 0396H      /* A/D0 control register 0 */
608
#pragma ADDRESS     ad0con1_addr 0397H      /* A/D0 control register 1 */
609
#pragma ADDRESS     da0_addr    0398H       /* D/A register 0 */
610
611
#pragma ADDRESS     da1_addr    039aH       /* D/A register 1 */
612
613
#pragma ADDRESS     dacon_addr  039cH       /* D/A control register */
614
#pragma ADDRESS     dacon1_addr 039dH       /* D/A control register 1 */
615
616
617
#pragma ADDRESS     ps8_addr    03a0H       /* Function select register A8 */
618
#pragma ADDRESS     ps9_addr    03a1H       /* Function select register A9 */
619
620
#pragma ADDRESS     psl9_addr   03a3H       /* Function select register B9 */
621
#pragma ADDRESS     pse2_addr   03a4H       /* Function select register E2 */
622
623
624
#pragma ADDRESS     psd1_addr   03a7H       /* Function select register D1 */
625
#pragma ADDRESS     psd2_addr   03a8H       /* Function select register D2 */
626
627
#pragma ADDRESS     psc6_addr   03aaH       /* Function select register C6 */
628
#pragma ADDRESS     pse1_addr   03abH       /* Function select register E1 */
629
#pragma ADDRESS     psc2_addr   03acH       /* Function select register C2 */
630
#pragma ADDRESS     psc3_addr   03adH       /* Function select register C3 */
631
632
#pragma ADDRESS     psc_addr    03afH       /* Function select register C */
633
#pragma ADDRESS     ps0_addr    03b0H       /* Function select register A0 */
634
#pragma ADDRESS     ps1_addr    03b1H       /* Function select register A1 */
635
#pragma ADDRESS     psl0_addr   03b2H       /* Function select register B0 */
636
#pragma ADDRESS     psl1_addr   03b3H       /* Function select register B1 */
637
#pragma ADDRESS     ps2_addr    03b4H       /* Function select register A2 */
638
#pragma ADDRESS     ps3_addr    03b5H       /* Function select register A3 */
639
#pragma ADDRESS     psl2_addr   03b6H       /* Function select register B2 */
640
#pragma ADDRESS     psl3_addr   03b7H       /* Function select register B3 */
641
#pragma ADDRESS     ps4_addr    03b8H       /* Function select register A4 */
642
#pragma ADDRESS     ps5_addr    03b9H       /* Function select register A5 */
643
644
645
#pragma ADDRESS     ps6_addr    03bcH       /* Function select register A6 */
646
#pragma ADDRESS     ps7_addr    03bdH       /* Function select register A7 */
647
#pragma ADDRESS     psl6_addr   03beH       /* Function select register B6 */
648
649
#pragma ADDRESS     p6_addr     03c0H       /* Port P6 register */
650
#pragma ADDRESS     p7_addr     03c1H       /* Port P7 register */
651
#pragma ADDRESS     pd6_addr    03c2H       /* Port P6 direction register */
652
#pragma ADDRESS     pd7_addr    03c3H       /* Port P7 direction register */
653
#pragma ADDRESS     p8_addr     03c4H       /* Port P8 register */
654
#pragma ADDRESS     p9_addr     03c5H       /* Port P9 register */
655
#pragma ADDRESS     pd8_addr    03c6H       /* Port P8 direction register */
656
#pragma ADDRESS     pd9_addr    03c7H       /* Port P9 direction register */
657
#pragma ADDRESS     p10_addr    03c8H       /* Port P10 register */
658
#pragma ADDRESS     p11_addr    03c9H       /* Port P11 register */
659
#pragma ADDRESS     pd10_addr   03caH       /* Port P10 direction register */
660
#pragma ADDRESS     pd11_addr   03cbH       /* Port P11 direction register */
661
#pragma ADDRESS     p12_addr    03ccH       /* Port P12 register */
662
#pragma ADDRESS     p13_addr    03cdH       /* Port P13 register */
663
#pragma ADDRESS     pd12_addr   03ceH       /* Port P12 direction register */
664
#pragma ADDRESS     pd13_addr   03cfH       /* Port P13 direction register */
665
#pragma ADDRESS     p14_addr    03d0H       /* Port P14 register */
666
#pragma ADDRESS     p15_addr    03d1H       /* Port P15 register */
667
#pragma ADDRESS     pd14_addr   03d2H       /* Port P14 direction register */
668
#pragma ADDRESS     pd15_addr   03d3H       /* Port P15 direction register */
669
670
671
#pragma ADDRESS     pur2_addr   03daH       /* Pull-up control register 2 */
672
#pragma ADDRESS     pur3_addr   03dbH       /* Pull-up control register 3 */
673
#pragma ADDRESS     pur4_addr   03dcH       /* Pull-up control register 4 */
674
675
676
#pragma ADDRESS     p0_addr     03e0H       /* Port P0 register */
677
#pragma ADDRESS     p1_addr     03e1H       /* Port P1 register */
678
#pragma ADDRESS     pd0_addr    03e2H       /* Port P0 direction register */
679
#pragma ADDRESS     pd1_addr    03e3H       /* Port P1 direction register */
680
#pragma ADDRESS     p2_addr     03e4H       /* Port P2 register */
681
#pragma ADDRESS     p3_addr     03e5H       /* Port P3 register */
682
#pragma ADDRESS     pd2_addr    03e6H       /* Port P2 direction register */
683
#pragma ADDRESS     pd3_addr    03e7H       /* Port P3 direction register */
684
#pragma ADDRESS     p4_addr     03e8H       /* Port P4 register */
685
#pragma ADDRESS     p5_addr     03e9H       /* Port P5 register */
686
#pragma ADDRESS     pd4_addr    03eaH       /* Port P4 direction register */
687
#pragma ADDRESS     pd5_addr    03ebH       /* Port P5 direction register */
688
689
690
#pragma ADDRESS     pur0_addr   03f0H       /* Pull-up control register 0 */
691
#pragma ADDRESS     pur1_addr   03f1H       /* Pull-up control register 1 */
692
693
694
#pragma ADDRESS     pcr_addr    03ffH       /* Port control register */
695
696
697
/*******************************************************
698
*   declare  SFR char                                   *
699
********************************************************/
700
unsigned char   da0_addr;               /* D/A register 0 */
701
#define     da0     da0_addr
702
703
unsigned char   da1_addr;               /* D/A register 1 */
704
#define     da1     da1_addr
705
706
/********************************************************
707
*   declare  SFR short                                  *
708
********************************************************/
709
/*---------------------------------------------------------------------
710
    Timer registers ; Read and write to this register in 16-bit units.
711
-----------------------------------------------------------------------*/
712
unsigned short   ta11_addr;             /* Timer A1-1 register */
713
#define     ta11     ta11_addr
714
715
unsigned short   ta21_addr;             /* Timer A2-1 register */
716
#define     ta21     ta21_addr
717
718
unsigned short   ta41_addr;             /* Timer A4-1 register */
719
#define     ta41     ta41_addr
720
721
unsigned short   tb3_addr;              /* Timer B3 register */
722
#define     tb3     tb3_addr
723
724
unsigned short   tb4_addr;              /* Timer B4 register */
725
#define     tb4     tb4_addr
726
727
unsigned short   tb5_addr;              /* Timer B5 register */
728
#define     tb5     tb5_addr
729
730
unsigned short   ta0_addr;              /* Timer A0 register */
731
#define     ta0     ta0_addr
732
733
unsigned short   ta1_addr;              /* Timer A1 register */
734
#define     ta1     ta1_addr
735
736
unsigned short   ta2_addr;              /* Timer A2 register */
737
#define     ta2     ta2_addr
738
739
unsigned short   ta3_addr;              /* Timer A3 register */
740
#define     ta3     ta3_addr
741
742
unsigned short   ta4_addr;              /* Timer A4 register */
743
#define     ta4     ta4_addr
744
745
unsigned short   tb0_addr;              /* Timer B0 register */
746
#define     tb0     tb0_addr
747
748
unsigned short   tb1_addr;              /* Timer B1 register */
749
#define     tb1     tb1_addr
750
751
unsigned short   tb2_addr;              /* Timer B2 register */
752
#define     tb2     tb2_addr
753
754
/*---------------------------------------------------------------------
755
    IIO registers ; Read and write to this register in 16-bit units.
756
-----------------------------------------------------------------------*/
757
758
/********************************************************
759
*   group 0 and 1 and 2                                 *
760
********************************************************/
761
#define     g1bt        g1bt_addr.word        /* Base Timer Register 1 */
762
#define     g1btl       g1bt_addr.byte.low
763
#define     g1bth       g1bt_addr.byte.high
764
765
#define     g1tm0        g1tm0_addr.word      /* Time Measurement Register 10 */
766
#define     g1tm0l       g1tm0_addr.byte.low
767
#define     g1tm0h       g1tm0_addr.byte.high
768
769
#define     g1tm1        g1tm1_addr.word      /* Time Measurement Register 11 */
770
#define     g1tm1l       g1tm1_addr.byte.low
771
#define     g1tm1h       g1tm1_addr.byte.high
772
773
#define     g1tm2        g1tm2_addr.word      /* Time Measurement Register 12 */
774
#define     g1tm2l       g1tm2_addr.byte.low
775
#define     g1tm2h       g1tm2_addr.byte.high
776
777
#define     g1tm3        g1tm3_addr.word      /* Time Measurement Register 13 */
778
#define     g1tm3l       g1tm3_addr.byte.low
779
#define     g1tm3h       g1tm3_addr.byte.high
780
781
#define     g1tm4        g1tm4_addr.word      /* Time Measurement Register 14 */
782
#define     g1tm4l       g1tm4_addr.byte.low
783
#define     g1tm4h       g1tm4_addr.byte.high
784
785
#define     g1tm5        g1tm5_addr.word      /* Time Measurement Register 15 */
786
#define     g1tm5l       g1tm5_addr.byte.low
787
#define     g1tm5h       g1tm5_addr.byte.high
788
789
#define     g1tm6        g1tm6_addr.word      /* Time Measurement Register 16 */
790
#define     g1tm6l       g1tm6_addr.byte.low
791
#define     g1tm6h       g1tm6_addr.byte.high
792
793
#define     g1tm7        g1tm7_addr.word      /* Time Measurement Register 17 */
794
#define     g1tm7l       g1tm7_addr.byte.low
795
#define     g1tm7h       g1tm7_addr.byte.high
796
797
#define     g1po0        g1po0_addr.word      /* Waveform Generate Register 10 */
798
#define     g1po0l       g1po0_addr.byte.low
799
#define     g1po0h       g1po0_addr.byte.high
800
801
#define     g1po1        g1po1_addr.word      /* Waveform Generate Register 11 */
802
#define     g1po1l       g1po1_addr.byte.low
803
#define     g1po1h       g1po1_addr.byte.high
804
805
#define     g1po2        g1po2_addr.word      /* Waveform Generate Register 12 */
806
#define     g1po2l       g1po2_addr.byte.low
807
#define     g1po2h       g1po2_addr.byte.high
808
809
#define     g1po3        g1po3_addr.word      /* Waveform Generate Register 13 */
810
#define     g1po3l       g1po3_addr.byte.low
811
#define     g1po3h       g1po3_addr.byte.high
812
813
#define     g1po4        g1po4_addr.word      /* Waveform Generate Register 14 */
814
#define     g1po4l       g1po4_addr.byte.low
815
#define     g1po4h       g1po4_addr.byte.high
816
817
#define     g1po5        g1po5_addr.word      /* Waveform Generate Register 15 */
818
#define     g1po5l       g1po5_addr.byte.low
819
#define     g1po5h       g1po5_addr.byte.high
820
821
#define     g1po6        g1po6_addr.word      /* Waveform Generate Register 16 */
822
#define     g1po6l       g1po6_addr.byte.low
823
#define     g1po6h       g1po6_addr.byte.high
824
825
#define     g1po7        g1po7_addr.word      /* Waveform Generate Register 17 */
826
#define     g1po7l       g1po7_addr.byte.low
827
#define     g1po7h       g1po7_addr.byte.high
828
829
#define     g2bt         g2bt_addr.word        /* Base Timer Register 2 */
830
#define     g2btl        g2bt_addr.byte.low
831
#define     g2bth        g2bt_addr.byte.high
832
833
#define     g2po0        g2po0_addr.word      /* Waveform Generate Register 20 */
834
#define     g2po0l       g2po0_addr.byte.low
835
#define     g2po0h       g2po0_addr.byte.high
836
837
#define     g2po1        g2po1_addr.word      /* Waveform Generate Register 21 */
838
#define     g2po1l       g2po1_addr.byte.low
839
#define     g2po1h       g2po1_addr.byte.high
840
841
#define     g2po2        g2po2_addr.word      /* Waveform Generate Register 22 */
842
#define     g2po2l       g2po2_addr.byte.low
843
#define     g2po2h       g2po2_addr.byte.high
844
845
#define     g2po3        g2po3_addr.word      /* Waveform Generate Register 23 */
846
#define     g2po3l       g2po3_addr.byte.low
847
#define     g2po3h       g2po3_addr.byte.high
848
849
#define     g2po4        g2po4_addr.word      /* Waveform Generate Register 24 */
850
#define     g2po4l       g2po4_addr.byte.low
851
#define     g2po4h       g2po4_addr.byte.high
852
853
#define     g2po5        g2po5_addr.word      /* Waveform Generate Register 25 */
854
#define     g2po5l       g2po5_addr.byte.low
855
#define     g2po5h       g2po5_addr.byte.high
856
857
#define     g2po6        g2po6_addr.word      /* Waveform Generate Register 26 */
858
#define     g2po6l       g2po6_addr.byte.low
859
#define     g2po6h       g2po6_addr.byte.high
860
861
#define     g2po7        g2po7_addr.word      /* Waveform Generate Register 27 */
862
#define     g2po7l       g2po7_addr.byte.low
863
#define     g2po7h       g2po7_addr.byte.high
864
865
#define     g0tcrc        g0tcrc_addr.word      /* Transmit CRC Code Register 0 */
866
#define     g0tcrcl       g0tcrc_addr.byte.low
867
#define     g0tcrch       g0tcrc_addr.byte.high
868
869
#define     g1tcrc        g1tcrc_addr.word      /* Transmit CRC Code Register 1 */
870
#define     g1tcrcl       g1tcrc_addr.byte.low
871
#define     g1tcrch       g1tcrc_addr.byte.high
872
873
#define     g0rcrc        g0rcrc_addr.word      /* Receive CRC Code Register 0 */
874
#define     g0rcrcl       g0rcrc_addr.byte.low
875
#define     g0rcrch       g0rcrc_addr.byte.high
876
877
#define     g1rcrc        g1rcrc_addr.word      /* Receive CRC Code Register 1 */
878
#define     g1rcrcl       g1rcrc_addr.byte.low
879
#define     g1rcrch       g1rcrc_addr.byte.high
880
881
/*------------------------------------------------------
882
    SI/O receive buffer register
883
------------------------------------------------------*/
884
885
/*------------------------------------------------------
886
     SI/O Receive Buffer Register 0
887
------------------------------------------------------*/
888
#define     g0rb        g0rb_addr.word
889
#define     g0rbl       g0rb_addr.byte.low
890
#define     g0rbh       g0rb_addr.byte.high
891
#define     oer_g0rb    g0rb_addr.bit.b12   /* Overrun error flag */
892
#define     fer_g0rb    g0rb_addr.bit.b13   /* Framing error flag */
893
894
/*------------------------------------------------------
895
     SI/O Receive Buffer Register 1
896
------------------------------------------------------*/
897
#define     g1rb        g1rb_addr.word
898
#define     g1rbl       g1rb_addr.byte.low
899
#define     g1rbh       g1rb_addr.byte.high
900
#define     oer_g1rb    g1rb_addr.bit.b12       /* Overrun error flag */
901
#define     fer_g1rb    g1rb_addr.bit.b13       /* Framing error flag */
902
903
/*------------------------------------------------------
904
     SI/O Receive Buffer Register 2
905
------------------------------------------------------*/
906
#define     g2rb        g2rb_addr.word
907
#define     g2rbl       g2rb_addr.byte.low
908
#define     g2rbh       g2rb_addr.byte.high
909
#define     oer_g2rb    g2rb_addr.bit.b12       /* Overrun error flag */
910
911
/*------------------------------------------------------
912
     SI/O Transmit Buffer Register 2
913
------------------------------------------------------*/
914
#define     g2tb        g2tb_addr.word
915
#define     g2tbl       g2tb_addr.byte.low
916
#define     g2tbh       g2tb_addr.byte.high
917
#define     a_g2tb      g2tb_addr.bit.b13
918
#define     pc_g2tb     g2tb_addr.bit.b14
919
#define     p_g2tb      g2tb_addr.bit.b15
920
921
/*------------------------------------------------------
922

923
------------------------------------------------------*/
924
#define     iear        iear_addr.word
925
#define     iearl       iear_addr.byte.low
926
#define     iearh       iear_addr.byte.high
927
928
/********************************************************
929
*   declare SFR bit                                     *
930
********************************************************/
931
struct bit_def {
932
        char    b0:1;
933
        char    b1:1;
934
        char    b2:1;
935
        char    b3:1;
936
        char    b4:1;
937
        char    b5:1;
938
        char    b6:1;
939
        char    b7:1;
940
};
941
union byte_def{
942
    struct bit_def bit;
943
    char    byte;
944
};
945
946
/*------------------------------------------------------
947
    External Space Wait Control Register 0
948
------------------------------------------------------*/
949
union byte_def ewcr0_addr;
950
#define     ewcr0      ewcr0_addr.byte
951
952
#define     ewcr000    ewcr0_addr.bit.b0    /* (b4-b0) Bus cycle select bit */
953
#define     ewcr001    ewcr0_addr.bit.b1
954
#define     ewcr002    ewcr0_addr.bit.b2
955
#define     ewcr003    ewcr0_addr.bit.b3
956
#define     ewcr004    ewcr0_addr.bit.b4
957
                                            /* (b5) Nothing is assigned */
958
#define     ewcr006    ewcr0_addr.bit.b6    /* Recovery cycle addition select bit */
959
                                            /* (b7) Nothing is assigned */
960
961
/*------------------------------------------------------
962
    External Space Wait Control Register 1
963
------------------------------------------------------*/
964
union byte_def ewcr1_addr;
965
#define     ewcr1      ewcr1_addr.byte
966
967
#define     ewcr100    ewcr1_addr.bit.b0    /* (b4-b0) Bus cycle select bit */
968
#define     ewcr101    ewcr1_addr.bit.b1
969
#define     ewcr102    ewcr1_addr.bit.b2
970
#define     ewcr103    ewcr1_addr.bit.b3
971
#define     ewcr104    ewcr1_addr.bit.b4
972
                                            /* (b5) Nothing is assigned */
973
#define     ewcr106    ewcr1_addr.bit.b6    /* Recovery cycle addition select bit */
974
                                            /* (b7) Nothing is assigned */
975
976
/*------------------------------------------------------
977
    External Space Wait Control Register 2
978
------------------------------------------------------*/
979
union byte_def ewcr2_addr;
980
#define     ewcr2      ewcr2_addr.byte
981
982
#define     ewcr200    ewcr2_addr.bit.b0    /* (b4-b0) Bus cycle select bit */
983
#define     ewcr201    ewcr2_addr.bit.b1
984
#define     ewcr202    ewcr2_addr.bit.b2
985
#define     ewcr203    ewcr2_addr.bit.b3
986
#define     ewcr204    ewcr2_addr.bit.b4
987
                                            /* (b5) Nothing is assigned */
988
#define     ewcr206    ewcr2_addr.bit.b6    /* Recovery cycle addition select bit */
989
                                            /* (b7) Nothing is assigned */
990
991
/*------------------------------------------------------
992
    External Space Wait Control Register 3
993
------------------------------------------------------*/
994
union byte_def ewcr3_addr;
995
#define     ewcr3      ewcr3_addr.byte
996
997
#define     ewcr300    ewcr3_addr.bit.b0    /* (b4-b0) Bus cycle select bit */
998
#define     ewcr301    ewcr3_addr.bit.b1
999
#define     ewcr302    ewcr3_addr.bit.b2
1000
#define     ewcr303    ewcr3_addr.bit.b3
1001
#define     ewcr304    ewcr3_addr.bit.b4
1002
                                            /* (b5) Nothing is assigned */
1003
#define     ewcr306    ewcr3_addr.bit.b6    /* Recovery cycle addition select bit */
1004
                                            /* (b7) Nothing is assigned */
1005
1006
/*------------------------------------------------------
1007
    Flash Memory control register 1
1008
------------------------------------------------------*/
1009
union byte_def fmr1_addr;
1010
#define     fmr1      fmr1_addr.byte
1011
                                            /* (b0) Reserved bit */
1012
#define     fmr11     fmr1_addr.bit.b1      /* EW1 mode select bit */
1013
                                            /* (b3-b2) Reserved bit */
1014
                                            /* (b5-b4) Reserved bit */
1015
#define     fmr16     fmr1_addr.bit.b6      /* Lock bit status flag */
1016
                                            /* (b7) Reserved bit (Set to 0) */
1017
1018
/*------------------------------------------------------
1019
    Flash Memory control register 0
1020
------------------------------------------------------*/
1021
#define     fmr       fmr_addr.word
1022
1023
union byte_def fmr0_addr;
1024
#define     fmr0      fmr0_addr.byte
1025
1026
#define     fmr00     fmr0_addr.bit.b0      /* RY/BY status flag */
1027
#define     fmr01     fmr0_addr.bit.b1      /* CPU rewrite mode select bit */
1028
#define     fmr02     fmr0_addr.bit.b2      /* Lock bit disable select bit */
1029
#define     fmstp     fmr0_addr.bit.b3      /* Flash memory stop bit */
1030
                                            /* (b4) Reserved bit (Set to 0) */
1031
#define     fmr05     fmr0_addr.bit.b5      /* User ROM area select bit (Available in boot mode only) */
1032
#define     fmr06     fmr0_addr.bit.b6      /* Program status flag */
1033
#define     fmr07     fmr0_addr.bit.b7      /* Erase status flag */
1034
1035
/*------------------------------------------------------
1036
    Processor mode register 0
1037
------------------------------------------------------*/
1038
union byte_def pm0_addr;
1039
#define     pm0     pm0_addr.byte
1040
1041
#define     pm00        pm0_addr.bit.b0     /* Processor mode bit */
1042
#define     pm01        pm0_addr.bit.b1     /* Processor mode bit */
1043
#define     pm02        pm0_addr.bit.b2     /* R/W mode select bit */
1044
#define     pm03        pm0_addr.bit.b3     /* Software reset bit */
1045
#define     pm04        pm0_addr.bit.b4     /* Multiplexed bus space select bit */
1046
#define     pm05        pm0_addr.bit.b5     /* Multiplexed bus space select bit */
1047
                                            /* (b6) Reserved bit (Set to 0) */
1048
#define     pm07        pm0_addr.bit.b7     /* BCLK output function select bit */
1049
1050
/*------------------------------------------------------
1051
    Processor mode register 1
1052
------------------------------------------------------*/
1053
union byte_def pm1_addr;
1054
#define     pm1     pm1_addr.byte
1055
1056
#define     pm10        pm1_addr.bit.b0     /* External memory area mode bit */
1057
#define     pm11        pm1_addr.bit.b1     /* External memory area mode bit */
1058
#define     pm12        pm1_addr.bit.b2     /* Internal memory wait bit */
1059
#define     pm13        pm1_addr.bit.b3     /* SFR wait bit */
1060
#define     pm14        pm1_addr.bit.b4     /* ALE pin select bit */
1061
#define     pm15        pm1_addr.bit.b5     /* ALE pin select bit */
1062
                                            /* (b7-b6) Reserved bit (Set to 0) */
1063
1064
/*------------------------------------------------------
1065
    Processor mode register 2
1066
------------------------------------------------------*/
1067
union byte_def pm2_addr;
1068
#define     pm2     pm2_addr.byte
1069
                                            /* (b0) Reserved bit (Set to 0) */
1070
#define     pm21        pm2_addr.bit.b1     /* System clock protect bit */
1071
#define     pm22        pm2_addr.bit.b2     /* WDT count source protect bit */
1072
                                            /* (b5-b3) Reserved bit (Set to 0) */
1073
#define     pm26        pm2_addr.bit.b6     /* (b7-b6) f2n count source select bit */
1074
#define     pm27        pm2_addr.bit.b7
1075
1076
/*------------------------------------------------------
1077
    System clock control register 0
1078
------------------------------------------------------*/
1079
union byte_def cm0_addr;
1080
#define     cm0     cm0_addr.byte
1081
1082
#define     cm00        cm0_addr.bit.b0     /* Clock output function select bit */
1083
#define     cm01        cm0_addr.bit.b1     /* Clock output function select bit */
1084
#define     cm02        cm0_addr.bit.b2     /* WAIT peripheral function clock stop bit */
1085
#define     cm03        cm0_addr.bit.b3     /* Xcin-Xcout drive capacity select bit */
1086
#define     cm04        cm0_addr.bit.b4     /* Port Xc select bit */
1087
#define     cm05        cm0_addr.bit.b5     /* Main clock stop bit */
1088
#define     cm06        cm0_addr.bit.b6     /* WDT function select bit */
1089
#define     cm07        cm0_addr.bit.b7     /* CPU clock select bit0 */
1090
1091
/*------------------------------------------------------
1092
    System clock control register 1
1093
------------------------------------------------------*/
1094
union byte_def cm1_addr;
1095
#define     cm1     cm1_addr.byte
1096
1097
#define     cm10        cm1_addr.bit.b0     /* All clock stop control bit */
1098
                                            /* (b4-b1) Reserved bit (Set to 0) */
1099
                                            /* (b5) Reserved bit (Set to 1) */
1100
                                            /* (b6) Reserved bit (Set to 0) */
1101
#define     cm17        cm1_addr.bit.b7     /* CPU clock select bit1 */
1102
1103
/*------------------------------------------------------
1104
    Oscillation stop detect register
1105
------------------------------------------------------*/
1106
union byte_def cm2_addr;
1107
#define     cm2     cm2_addr.byte
1108
1109
#define     cm20        cm2_addr.bit.b0     /* Oscillation stop detect enable bit */
1110
#define     cm21        cm2_addr.bit.b1     /* CPU clock select bit2 */
1111
#define     cm22        cm2_addr.bit.b2     /* Oscillation stop detect flag */
1112
#define     cm23        cm2_addr.bit.b3     /* Main clock monitor flag */
1113
                                            /* (b7-b4) Reserved bit (Set to 0) */
1114
1115
1116
/*------------------------------------------------------
1117
    Address match interrupt enable register
1118
------------------------------------------------------*/
1119
union byte_def aier_addr;
1120
#define     aier        aier_addr.byte
1121
1122
#define     aier0       aier_addr.bit.b0    /* Address match interrupt 0 enable bit */
1123
#define     aier1       aier_addr.bit.b1    /* Address match interrupt 1 enable bit */
1124
#define     aier2       aier_addr.bit.b2    /* Address match interrupt 2 enable bit */
1125
#define     aier3       aier_addr.bit.b3    /* Address match interrupt 3 enable bit */
1126
#define     aier4       aier_addr.bit.b4    /* Address match interrupt 4 enable bit */
1127
#define     aier5       aier_addr.bit.b5    /* Address match interrupt 5 enable bit */
1128
#define     aier6       aier_addr.bit.b6    /* Address match interrupt 6 enable bit */
1129
#define     aier7       aier_addr.bit.b7    /* Address match interrupt 7 enable bit */
1130
1131
/*------------------------------------------------------
1132
    X-Y control register
1133
------------------------------------------------------*/
1134
union byte_def xyc_addr;
1135
#define     xyc     xyc_addr.byte
1136
1137
#define     xyc0        xyc_addr.bit.b0     /* Read-mode set bit */
1138
#define     xyc1        xyc_addr.bit.b1     /* Write-mode set bit */
1139
                                            /* (b7-b2) Nothing is assigned */
1140
1141
/*------------------------------------------------------
1142
    Protect register
1143
------------------------------------------------------*/
1144
union byte_def prcr_addr;
1145
#define     prcr        prcr_addr.byte
1146
1147
#define     prc0        prcr_addr.bit.b0    /* Protect bit0 */
1148
#define     prc1        prcr_addr.bit.b1    /* Protect bit1 */
1149
#define     prc2        prcr_addr.bit.b2    /* Protect bit2 */
1150
#define     prc3        prcr_addr.bit.b3    /* Protect bit3 */
1151
                                            /* (b7-b4) Nothing is assigned */
1152
1153
/*------------------------------------------------------
1154
    External data bus width control register
1155
------------------------------------------------------*/
1156
union byte_def ds_addr;
1157
#define     ds      ds_addr.byte
1158
1159
#define     ds0     ds_addr.bit.b0          /* External space 0 data bus width select bit */
1160
#define     ds1     ds_addr.bit.b1          /* External space 1 data bus width select bit */
1161
#define     ds2     ds_addr.bit.b2          /* External space 2 data bus width select bit */
1162
#define     ds3     ds_addr.bit.b3          /* External space 3 data bus width select bit */
1163
                                            /* (b7-b4) Nothing is assigned */
1164
1165
/*------------------------------------------------------
1166
    Main clock division register
1167
------------------------------------------------------*/
1168
union byte_def mcd_addr;
1169
#define     mcd     mcd_addr.byte
1170
1171
#define     mcd0        mcd_addr.bit.b0     /* (b4-b0) Main clock division select bit */
1172
#define     mcd1        mcd_addr.bit.b1
1173
#define     mcd2        mcd_addr.bit.b2
1174
#define     mcd3        mcd_addr.bit.b3
1175
#define     mcd4        mcd_addr.bit.b4
1176
                                            /* (b7-b5) Reserved bit (Set to 0) */
1177
1178
/*------------------------------------------------------
1179
   Count source prescaler register
1180
------------------------------------------------------*/
1181
union byte_def tcspr_addr;
1182
#define     tcspr     tcspr_addr.byte
1183
1184
#define     cnt0        tcspr_addr.bit.b0   /* (b3-b0) Divide ratio select bit */
1185
#define     cnt1        tcspr_addr.bit.b1
1186
#define     cnt2        tcspr_addr.bit.b2
1187
#define     cnt3        tcspr_addr.bit.b3
1188
                                            /* (b6-b4) Reserved bit (Set to 0) */
1189
#define     cst         tcspr_addr.bit.b7   /* Operation enable bit */
1190
1191
/*------------------------------------------------------
1192
    Exit priority register
1193
------------------------------------------------------*/
1194
union byte_def rlvl_addr;
1195
#define     rlvl        rlvl_addr.byte
1196
1197
#define     rlvl0       rlvl_addr.bit.b0    /* (b2-b0) Interrupt priority set bits to exit STOP/WAIT mode */
1198
#define     rlvl1       rlvl_addr.bit.b1
1199
#define     rlvl2       rlvl_addr.bit.b2
1200
#define     fsit        rlvl_addr.bit.b3    /* High-speed interrupt set bit */
1201
                                            /* (b4) Nothing is assigned */
1202
#define     dmaii       rlvl_addr.bit.b5    /* DMAC II select bit */
1203
                                            /* (b7-b6) Nothing is assigned */
1204
1205
/*------------------------------------------------------
1206
    External interrupt request cause select register 1
1207
------------------------------------------------------*/
1208
union byte_def ifsra_addr;
1209
#define     ifsra        ifsra_addr.byte
1210
1211
#define     ifsr10      ifsra_addr.bit.b0   /* INT6 interrupt polarity select bit */
1212
#define     ifsr11      ifsra_addr.bit.b1   /* INT7 interrupt polarity select bit */
1213
#define     ifsr12      ifsra_addr.bit.b2   /* INT8 interrupt polarity select bit */
1214
                                            /* (b7-b3) Reserved bit (Set to 0) */
1215
1216
/*------------------------------------------------------
1217
    External interrupt request cause select register
1218
------------------------------------------------------*/
1219
union byte_def ifsr_addr;
1220
#define     ifsr        ifsr_addr.byte
1221
1222
#define     ifsr0       ifsr_addr.bit.b0    /* INT0 interrupt polarity select bit */
1223
#define     ifsr1       ifsr_addr.bit.b1    /* INT1 interrupt polarity select bit */
1224
#define     ifsr2       ifsr_addr.bit.b2    /* INT2 interrupt polarity select bit */
1225
#define     ifsr3       ifsr_addr.bit.b3    /* INT3 interrupt polarity select bit */
1226
#define     ifsr4       ifsr_addr.bit.b4    /* INT4 interrupt polarity select bit */
1227
#define     ifsr5       ifsr_addr.bit.b5    /* INT5 interrupt polarity select bit */
1228
#define     ifsr6       ifsr_addr.bit.b6    /* UART0,3 interrupt cause select bit */
1229
#define     ifsr7       ifsr_addr.bit.b7    /* UART1,4 interrupt cause select bit */
1230
1231
/*------------------------------------------------------
1232
    Timer B2 special mode register
1233
------------------------------------------------------*/
1234
union byte_def tb2sc_addr;
1235
#define     tb2sc     tb2sc_addr.byte
1236
1237
#define     pwcon     tb2sc_addr.bit.b0     /* Timer B2 reload timing switching bit */
1238
                                            /* (b7-b1) Nothing is assigned */
1239
1240
/*------------------------------------------------------
1241
    Watchdog timer start register
1242
------------------------------------------------------*/
1243
union byte_def wdts_addr;
1244
#define     wdts        wdts_addr.byte
1245
1246
/*------------------------------------------------------
1247
    CRC input register
1248
------------------------------------------------------*/
1249
union byte_def crcin_addr;
1250
#define     crcin       crcin_addr.byte
1251
1252
/*------------------------------------------------------
1253
    Watchdog timer control register
1254
------------------------------------------------------*/
1255
union byte_def wdc_addr;
1256
#define     wdc     wdc_addr.byte
1257
1258
                                            /* (b4-b0) High-order bits of the watchdog timer */
1259
#define     wdc5        wdc_addr.bit.b5     /* Cold start/warm start detect flag */
1260
                                            /* (b6) Reserved bit (Set to 0) */
1261
#define     wdc7        wdc_addr.bit.b7     /* Prescaler select bit */
1262
1263
/*------------------------------------------------------
1264
    Voltage detection register 1
1265
------------------------------------------------------*/
1266
union byte_def vcr1_addr;
1267
#define     vcr1     vcr1_addr.byte
1268
                                            /* (b2-b0) Reserved bit (Set to 0) */
1269
#define     vc13        vcr1_addr.bit.b3    /* Voltage down monitor flag */
1270
                                            /* (b7-b4) Reserved bit (Set to 0) */
1271
1272
/*------------------------------------------------------
1273
    Voltage detection register 2
1274
------------------------------------------------------*/
1275
union byte_def vcr2_addr;
1276
#define     vcr2     vcr2_addr.byte
1277
                                            /* (b5-b0) Reserved bit (Set to 0) */
1278
#define     vc26        vcr2_addr.bit.b6    /* Reset level monitor bit */
1279
#define     vc27        vcr2_addr.bit.b7    /* Voltage down monitor bit */
1280
1281
/*------------------------------------------------------
1282
    Count start flag
1283
------------------------------------------------------*/
1284
union byte_def tabsr_addr;
1285
#define     tabsr       tabsr_addr.byte
1286
1287
#define     ta0s        tabsr_addr.bit.b0   /* Timer A0 count start flag */
1288
#define     ta1s        tabsr_addr.bit.b1   /* Timer A1 count start flag */
1289
#define     ta2s        tabsr_addr.bit.b2   /* Timer A2 count start flag */
1290
#define     ta3s        tabsr_addr.bit.b3   /* Timer A3 count start flag */
1291
#define     ta4s        tabsr_addr.bit.b4   /* Timer A4 count start flag */
1292
#define     tb0s        tabsr_addr.bit.b5   /* Timer B0 count start flag */
1293
#define     tb1s        tabsr_addr.bit.b6   /* Timer B1 count start flag */
1294
#define     tb2s        tabsr_addr.bit.b7   /* Timer B2 count start flag */
1295
1296
/*------------------------------------------------------
1297
    Timer B3,4,5 count start flag
1298
------------------------------------------------------*/
1299
union byte_def tbsr_addr;
1300
#define     tbsr        tbsr_addr.byte
1301
                                            /* (b4-b0) Nothing is assigned */
1302
#define     tb3s        tbsr_addr.bit.b5    /* Timer B3 count start flag */
1303
#define     tb4s        tbsr_addr.bit.b6    /* Timer B4 count start flag */
1304
#define     tb5s        tbsr_addr.bit.b7    /* Timer B5 count start flag */
1305
1306
/*------------------------------------------------------
1307
    Three-phase PWM control register 0
1308
------------------------------------------------------*/
1309
union byte_def invc0_addr;
1310
#define     invc0       invc0_addr.byte
1311
1312
#define     inv00       invc0_addr.bit.b0   /* Interrupt enable output polarity select bit */
1313
#define     inv01       invc0_addr.bit.b1   /* Interrupt enable output specification bit */
1314
#define     inv02       invc0_addr.bit.b2   /* Mode select bit */
1315
#define     inv03       invc0_addr.bit.b3   /* Output control bit */
1316
#define     inv04       invc0_addr.bit.b4   /* Positive & negative phases concurrent active disable function enable bit */
1317
#define     inv05       invc0_addr.bit.b5   /* Positive & negative phases concurrent active output detect flag */
1318
#define     inv06       invc0_addr.bit.b6   /* Modulation mode select bit */
1319
#define     inv07       invc0_addr.bit.b7   /* Software trigger select bit */
1320
1321
/*------------------------------------------------------
1322
    Three-phase PWM control register 1
1323
------------------------------------------------------*/
1324
union byte_def invc1_addr;
1325
#define     invc1       invc1_addr.byte
1326
1327
#define     inv10       invc1_addr.bit.b0   /* Timer A1,A2 and A4 start trigger select bit */
1328
#define     inv11       invc1_addr.bit.b1   /* Timer A1-1,A2-1,A4-1 control bit */
1329
#define     inv12       invc1_addr.bit.b2   /* Dead time timer count source select bit */
1330
#define     inv13       invc1_addr.bit.b3   /* Carrier wave detect flag */
1331
#define     inv14       invc1_addr.bit.b4   /* Output polarity control bit */
1332
#define     inv15       invc1_addr.bit.b5   /* Dead time disable bit */
1333
#define     inv16       invc1_addr.bit.b6   /* Dead time timer trigger select bit */
1334
                                            /* (b7) Reserved bit (Set to 0) */
1335
1336
/*------------------------------------------------------
1337
    Three-phase output buffer register 0
1338
------------------------------------------------------*/
1339
union byte_def idb0_addr;
1340
#define     idb0        idb0_addr.byte
1341
1342
#define     du0         idb0_addr.bit.b0    /*  U-phase output buffer 0 */
1343
#define     dub0        idb0_addr.bit.b1    /* ~U-phase output buffer 0 */
1344
#define     dv0         idb0_addr.bit.b2    /*  V-phase output buffer 0 */
1345
#define     dvb0        idb0_addr.bit.b3    /* ~V-phase output buffer 0 */
1346
#define     dw0         idb0_addr.bit.b4    /*  W-phase output buffer 0 */
1347
#define     dwb0        idb0_addr.bit.b5    /* ~W-phase output buffer 0 */
1348
                                            /* (b7-b6) Reserved bit (Set to 0) */
1349
1350
/*------------------------------------------------------
1351
    Three-phase output buffer register 1
1352
------------------------------------------------------*/
1353
union byte_def idb1_addr;
1354
#define     idb1        idb1_addr.byte
1355
1356
#define     du1         idb1_addr.bit.b0    /*  U-phase output buffer 1 */
1357
#define     dub1        idb1_addr.bit.b1    /* ~U-phase output buffer 1 */
1358
#define     dv1         idb1_addr.bit.b2    /*  V-phase output buffer 1 */
1359
#define     dvb1        idb1_addr.bit.b3    /* ~V-phase output buffer 1 */
1360
#define     dw1         idb1_addr.bit.b4    /*  W-phase output buffer 1 */
1361
#define     dwb1        idb1_addr.bit.b5    /* ~W-phase output buffer 1 */
1362
                                            /* (b7-b6) Reserved bit (Set to 0) */
1363
1364
1365
/*------------------------------------------------------
1366
     Dead time timer
1367
        (1) The MOV instruction should be used to set the DTT register
1368
------------------------------------------------------*/
1369
union byte_def dtt_addr;
1370
#define     dtt     dtt_addr.byte
1371
1372
/*------------------------------------------------------
1373
    Timer B2 interrupt generation frequency set counter
1374
        (1) The MOV instruction should be used to the ICTB2 register
1375
------------------------------------------------------*/
1376
union byte_def ictb2_addr;
1377
#define     ictb2       ictb2_addr.byte     /* (b3-b0) function */
1378
                                            /* (b7-b4) Nothing is assigned */
1379
1380
/*------------------------------------------------------
1381
    One-shot start flag
1382
------------------------------------------------------*/
1383
union byte_def onsf_addr;
1384
#define     onsf        onsf_addr.byte
1385
1386
#define     ta0os       onsf_addr.bit.b0    /* Timer A0 one-shot start flag */
1387
#define     ta1os       onsf_addr.bit.b1    /* Timer A1 one-shot start flag */
1388
#define     ta2os       onsf_addr.bit.b2    /* Timer A2 one-shot start flag */
1389
#define     ta3os       onsf_addr.bit.b3    /* Timer A3 one-shot start flag */
1390
#define     ta4os       onsf_addr.bit.b4    /* Timer A4 one-shot start flag */
1391
#define     tazie       onsf_addr.bit.b5    /* Z-phase input enable bit */
1392
#define     ta0tgl      onsf_addr.bit.b6    /* Timer A0 event/trigger select bit */
1393
#define     ta0tgh      onsf_addr.bit.b7    /* Timer A0 event/trigger select bit */
1394
1395
/*------------------------------------------------------
1396
    Clock prescaler reset flag
1397
------------------------------------------------------*/
1398
union byte_def cpsrf_addr;
1399
#define     cpsrf       cpsrf_addr.byte
1400
                                            /* (b6-b0) Nothing is assigned */
1401
#define     cpsr        cpsrf_addr.bit.b7   /* Clock prescaler reset flag */
1402
1403
/*------------------------------------------------------
1404
    Trigger select register
1405
------------------------------------------------------*/
1406
union byte_def trgsr_addr;
1407
#define     trgsr       trgsr_addr.byte
1408
1409
#define     ta1tgl      trgsr_addr.bit.b0   /* Timer A1 event/trigger select bit */
1410
#define     ta1tgh      trgsr_addr.bit.b1   /* Timer A1 event/trigger select bit */
1411
#define     ta2tgl      trgsr_addr.bit.b2   /* Timer A2 event/trigger select bit */
1412
#define     ta2tgh      trgsr_addr.bit.b3   /* Timer A2 event/trigger select bit */
1413
#define     ta3tgl      trgsr_addr.bit.b4   /* Timer A3 event/trigger select bit */
1414
#define     ta3tgh      trgsr_addr.bit.b5   /* Timer A3 event/trigger select bit */
1415
#define     ta4tgl      trgsr_addr.bit.b6   /* Timer A4 event/trigger select bit */
1416
#define     ta4tgh      trgsr_addr.bit.b7   /* Timer A4 event/trigger select bit */
1417
1418
/*------------------------------------------------------
1419
    Up Down Flag
1420
        (1) The MOV instruction should be used to set the UDF register
1421
------------------------------------------------------*/
1422
union byte_def   udf_addr;               /* Up/down flag */
1423
#define     udf     udf_addr.byte
1424
1425
#define     ta0ud   udf_addr.bit.b0     /* Timer A0 up/down flag */
1426
#define     ta1ud   udf_addr.bit.b1     /* Timer A1 up/down flag */
1427
#define     ta2ud   udf_addr.bit.b2     /* Timer A2 up/down flag */
1428
#define     ta3ud   udf_addr.bit.b3     /* Timer A3 up/down flag */
1429
#define     ta4ud   udf_addr.bit.b4     /* Timer A4 up/down flag */
1430
#define     ta2p    udf_addr.bit.b5     /* Timer A2 2-phase pulse signal processing function select bit */
1431
#define     ta3p    udf_addr.bit.b6     /* Timer A3 2-phase pulse signal processing function select bit */
1432
#define     ta4p    udf_addr.bit.b7     /* Timer A4 2-phase pulse signal processing function select bit */
1433
1434
/*------------------------------------------------------
1435
    UARTi transmit/receive control register 1 (i=0,1,2,3,4)
1436
------------------------------------------------------*/
1437
/*------------------------------------------------------
1438
    u0c1
1439
------------------------------------------------------*/
1440
union byte_def u0c1_addr;
1441
#define     u0c1            u0c1_addr.byte
1442
#define     te_u0c1         u0c1_addr.bit.b0    /* Transmit enable bit */
1443
#define     ti_u0c1         u0c1_addr.bit.b1    /* Transmit buffer empty flag */
1444
#define     re_u0c1         u0c1_addr.bit.b2    /* Receive enable bit */
1445
#define     ri_u0c1         u0c1_addr.bit.b3    /* Receive complete flag */
1446
#define     u0irs_u0c1      u0c1_addr.bit.b4    /* UARTi transmit interrupt cause select bit */
1447
#define     u0rrm_u0c1      u0c1_addr.bit.b5    /* UARTi continuous receive mode enable bit */
1448
#define     u0lch_u0c1      u0c1_addr.bit.b6    /* Data logic select bit */
1449
#define     sclkstpb_u0c1   u0c1_addr.bit.b7    /* Clock divide synchronizing stop bit */
1450
#define     u0ere_u0c1      u0c1_addr.bit.b7    /* Error signal output enable bit */
1451
1452
/*------------------------------------------------------
1453
    u1c1
1454
------------------------------------------------------*/
1455
union byte_def u1c1_addr;
1456
#define     u1c1            u1c1_addr.byte
1457
#define     te_u1c1         u1c1_addr.bit.b0
1458
#define     ti_u1c1         u1c1_addr.bit.b1
1459
#define     re_u1c1         u1c1_addr.bit.b2
1460
#define     ri_u1c1         u1c1_addr.bit.b3
1461
#define     u1irs_u1c1      u1c1_addr.bit.b4
1462
#define     u1rrm_u1c1      u1c1_addr.bit.b5
1463
#define     u1lch_u1c1      u1c1_addr.bit.b6
1464
#define     sclkstpb_u1c1   u1c1_addr.bit.b7
1465
#define     u1ere_u1c1      u1c1_addr.bit.b7
1466
1467
/*------------------------------------------------------
1468
    u2c1
1469
------------------------------------------------------*/
1470
union byte_def u2c1_addr;
1471
#define     u2c1            u2c1_addr.byte
1472
#define     te_u2c1         u2c1_addr.bit.b0
1473
#define     ti_u2c1         u2c1_addr.bit.b1
1474
#define     re_u2c1         u2c1_addr.bit.b2
1475
#define     ri_u2c1         u2c1_addr.bit.b3
1476
#define     u2irs_u2c1      u2c1_addr.bit.b4
1477
#define     u2rrm_u2c1      u2c1_addr.bit.b5
1478
#define     u2lch_u2c1      u2c1_addr.bit.b6
1479
#define     sclkstpb_u2c1   u2c1_addr.bit.b7
1480
#define     u2ere_u2c1      u2c1_addr.bit.b7
1481
1482
/*------------------------------------------------------
1483
    u3c1
1484
------------------------------------------------------*/
1485
union byte_def u3c1_addr;
1486
#define     u3c1            u3c1_addr.byte
1487
#define     te_u3c1         u3c1_addr.bit.b0
1488
#define     ti_u3c1         u3c1_addr.bit.b1
1489
#define     re_u3c1         u3c1_addr.bit.b2
1490
#define     ri_u3c1         u3c1_addr.bit.b3
1491
#define     u3irs_u3c1      u3c1_addr.bit.b4
1492
#define     u3rrm_u3c1      u3c1_addr.bit.b5
1493
#define     u3lch_u3c1      u3c1_addr.bit.b6
1494
#define     sclkstpb_u3c1   u3c1_addr.bit.b7
1495
#define     u3ere_u3c1      u3c1_addr.bit.b7
1496
1497
/*------------------------------------------------------
1498
    u4c1
1499
------------------------------------------------------*/
1500
union byte_def u4c1_addr;
1501
#define     u4c1            u4c1_addr.byte
1502
#define     te_u4c1         u4c1_addr.bit.b0
1503
#define     ti_u4c1         u4c1_addr.bit.b1
1504
#define     re_u4c1         u4c1_addr.bit.b2
1505
#define     ri_u4c1         u4c1_addr.bit.b3
1506
#define     u4irs_u4c1      u4c1_addr.bit.b4
1507
#define     u4rrm_u4c1      u4c1_addr.bit.b5
1508
#define     u4lch_u4c1      u4c1_addr.bit.b6
1509
#define     sclkstpb_u4c1   u4c1_addr.bit.b7
1510
#define     u4ere_u4c1      u4c1_addr.bit.b7
1511
1512
/*------------------------------------------------------
1513
    u5c1
1514
------------------------------------------------------*/
1515
union byte_def u5c1_addr;
1516
#define     u5c1            u5c1_addr.byte
1517
#define     te_u5c1         u5c1_addr.bit.b0
1518
#define     ti_u5c1         u5c1_addr.bit.b1
1519
#define     re_u5c1         u5c1_addr.bit.b2
1520
#define     ri_u5c1         u5c1_addr.bit.b3
1521
                                                 /* (b7-b4) Nothing is assigned */
1522
1523
/*------------------------------------------------------
1524
    u6c1
1525
------------------------------------------------------*/
1526
union byte_def u6c1_addr;
1527
#define     u6c1            u6c1_addr.byte
1528
#define     te_u6c1         u6c1_addr.bit.b0
1529
#define     ti_u6c1         u6c1_addr.bit.b1
1530
#define     re_u6c1         u6c1_addr.bit.b2
1531
#define     ri_u6c1         u6c1_addr.bit.b3
1532
                                                 /* (b7-b4) Nothing is assigned */
1533
1534
/*------------------------------------------------------
1535

1536
------------------------------------------------------*/
1537
union byte_def ircon_addr;
1538
#define     ircon           ircon_addr.byte
1539
#define     irsel           ircon_addr.bit.b0
1540
#define     plssel          ircon_addr.bit.b1
1541
#define     irtpol          ircon_addr.bit.b2
1542
#define     irrpol          ircon_addr.bit.b3
1543
#define     irpd0           ircon_addr.bit.b4
1544
#define     irpd1           ircon_addr.bit.b5
1545
#define     irck            ircon_addr.bit.b6
1546
                                                 /* (b7) Nothing is assigned */
1547
1548
/*------------------------------------------------------
1549

1550
------------------------------------------------------*/
1551
union byte_def u56con_addr;
1552
#define     u56con          u56con_addr.byte
1553
#define     u5irs           u56con_addr.bit.b0
1554
#define     u6irs           u56con_addr.bit.b1
1555
#define     u5rrm           u56con_addr.bit.b2
1556
#define     u6rrm           u56con_addr.bit.b3
1557
                                            /* (b7-b4) Reserved bit (Set to 0) */
1558
1559
/*------------------------------------------------------
1560

1561
------------------------------------------------------*/
1562
union byte_def u56is_addr;
1563
#define     u56is           u56is_addr.byte
1564
#define     u5clk           u56is_addr.bit.b0
1565
#define     u5rxd           u56is_addr.bit.b1
1566
#define     u5cts           u56is_addr.bit.b2
1567
                                                 /* (b3) Nothing is assigned */
1568
#define     u6clk           u56is_addr.bit.b4
1569
#define     u6rxd           u56is_addr.bit.b5
1570
#define     u6cts           u56is_addr.bit.b6
1571
                                                 /* (b7) Nothing is assigned */
1572
1573
/*------------------------------------------------------
1574

1575
------------------------------------------------------*/
1576
union byte_def rtp0r_addr;
1577
#define     rtp0r           rtp0r_addr.byte
1578
#define     rtp00           rtp0r_addr.bit.b0
1579
#define     rtp01           rtp0r_addr.bit.b1
1580
#define     rtp02           rtp0r_addr.bit.b2
1581
                                                 /* (b7-b3) Nothing is assigned */
1582
/*------------------------------------------------------
1583

1584
------------------------------------------------------*/
1585
union byte_def rtp1r_addr;
1586
#define     rtp1r           rtp1r_addr.byte
1587
#define     rtp10           rtp1r_addr.bit.b0
1588
#define     rtp11           rtp1r_addr.bit.b1
1589
#define     rtp12           rtp1r_addr.bit.b2
1590
                                                 /* (b7-b3) Nothing is assigned */
1591
/*------------------------------------------------------
1592

1593
------------------------------------------------------*/
1594
union byte_def rtp2r_addr;
1595
#define     rtp2r           rtp2r_addr.byte
1596
#define     rtp20           rtp2r_addr.bit.b0
1597
#define     rtp21           rtp2r_addr.bit.b1
1598
#define     rtp22           rtp2r_addr.bit.b2
1599
                                                 /* (b7-b3) Nothing is assigned */
1600
/*------------------------------------------------------
1601

1602
------------------------------------------------------*/
1603
union byte_def rtp3r_addr;
1604
#define     rtp3r           rtp3r_addr.byte
1605
#define     rtp30           rtp3r_addr.bit.b0
1606
#define     rtp31           rtp3r_addr.bit.b1
1607
#define     rtp32           rtp3r_addr.bit.b2
1608
                                                 /* (b7-b3) Nothing is assigned */
1609
1610
/*------------------------------------------------------
1611
    A/D0 control register 0
1612
------------------------------------------------------*/
1613
union byte_def ad0con0_addr;
1614
#define     ad0con0      ad0con0_addr.byte
1615
1616
#define     ch0_ad0con0     ad0con0_addr.bit.b0  /* Analog input pin select bit */
1617
#define     ch1_ad0con0     ad0con0_addr.bit.b1  /* Analog input pin select bit */
1618
#define     ch2_ad0con0     ad0con0_addr.bit.b2  /* Analog input pin select bit */
1619
#define     md0_ad0con0     ad0con0_addr.bit.b3  /* A/D operation mode select bit 0 */
1620
#define     md1_ad0con0     ad0con0_addr.bit.b4  /* A/D operation mode select bit 0 */
1621
#define     trg_ad0con0     ad0con0_addr.bit.b5  /* Trigger select bit */
1622
#define     adst_ad0con0    ad0con0_addr.bit.b6  /* A/D conversion start flag */
1623
#define     cks0_ad0con0    ad0con0_addr.bit.b7  /* Frequency select bit 0 */
1624
1625
/*------------------------------------------------------
1626
    A/D0 control  register 1
1627
------------------------------------------------------*/
1628
union byte_def ad0con1_addr;
1629
#define     ad0con1      ad0con1_addr.byte
1630
1631
#define     scan0_ad0con1   ad0con1_addr.bit.b0  /* A/D sweep pin select bit */
1632
#define     scan1_ad0con1   ad0con1_addr.bit.b1  /* A/D sweep pin select bit */
1633
#define     md2_ad0con1     ad0con1_addr.bit.b2  /* A/D operation mode select bit 1 */
1634
#define     bits_ad0con1    ad0con1_addr.bit.b3  /* 8/10-bit mode select bit */
1635
#define     cks1_ad0con1    ad0con1_addr.bit.b4  /* Frequency select bit 1 */
1636
#define     vcut_ad0con1    ad0con1_addr.bit.b5  /* Vref connection bit */
1637
#define     opa0_ad0con1    ad0con1_addr.bit.b6  /* External op-amp connection mode bit */
1638
#define     opa1_ad0con1    ad0con1_addr.bit.b7  /* External op-amp connection mode bit */
1639
1640
/*------------------------------------------------------
1641
    A/D0 control register 2
1642
------------------------------------------------------*/
1643
union byte_def ad0con2_addr;
1644
#define     ad0con2      ad0con2_addr.byte
1645
1646
#define     smp_ad0con2     ad0con2_addr.bit.b0  /* A/D conversion method select bit */
1647
#define     aps0_ad0con2    ad0con2_addr.bit.b1  /* Analog input port select bit */
1648
#define     aps1_ad0con2    ad0con2_addr.bit.b2  /* Analog input port select bit */
1649
                                                 /* (b4-b3) Nothing is assigned */
1650
#define     trg0_ad0con2    ad0con2_addr.bit.b5  /* External trigger request cause select bit */
1651
                                                 /* (b7-b6) Reserved bit (Set to 0) */
1652
1653
/*------------------------------------------------------
1654
    A/D0 Control Register 3
1655
------------------------------------------------------*/
1656
union byte_def ad0con3_addr;
1657
#define     ad0con3      ad0con3_addr.byte
1658
1659
#define     dus_ad0con3     ad0con3_addr.bit.b0  /* DMAC operation select bit */
1660
#define     mss_ad0con3     ad0con3_addr.bit.b1  /* Multi-port sweep mode select bit */
1661
#define     cks2_ad0con3    ad0con3_addr.bit.b2  /* Frequency select bit */
1662
#define     msf0_ad0con3    ad0con3_addr.bit.b3  /* Multi-port sweep status flag */
1663
#define     msf1_ad0con3    ad0con3_addr.bit.b4  /* Multi-port sweep status flag */
1664
                                                 /* (b7-b5):Reserved bit (Set to 0) */
1665
1666
/*------------------------------------------------------
1667
    A/D0 Control Register 4
1668
------------------------------------------------------*/
1669
union byte_def ad0con4_addr;
1670
#define     ad0con4      ad0con4_addr.byte
1671
                                                /* (b1-b0) Reserved bit (Set to 0) */
1672
#define     mps10_ad0con4   ad0con4_addr.bit.b2 /* Multi-port sweep port select bit */
1673
#define     mps11_ad0con4   ad0con4_addr.bit.b3 /* Multi-port sweep port select bit */
1674
                                                /* (b7-b4) Reserved bit (Set to 0) */
1675
1676
/*------------------------------------------------------
1677
    D/A control register
1678
------------------------------------------------------*/
1679
union byte_def dacon_addr;
1680
#define     dacon       dacon_addr.byte
1681
1682
#define     da0e        dacon_addr.bit.b0   /* D/A0 output enable bit */
1683
#define     da1e        dacon_addr.bit.b1   /* D/A1 output enable bit */
1684
                                            /* (b7-b2) Nothing is assigned */
1685
1686
/*------------------------------------------------------
1687
    D/A control register 1
1688
------------------------------------------------------*/
1689
union byte_def dacon1_addr;
1690
#define     dacon1      dacon1_addr.byte
1691
1692
#define     dat00       dacon1_addr.bit.b0
1693
#define     dat01       dacon1_addr.bit.b1
1694
#define     dat10       dacon1_addr.bit.b2
1695
#define     dat11       dacon1_addr.bit.b3
1696
                                            /* (b7-b4) Nothing is assigned */
1697
1698
/*------------------------------------------------------
1699
    SI/O Communication Mode Register 0
1700
------------------------------------------------------*/
1701
union byte_def g0mr_addr;
1702
#define     g0mr    g0mr_addr.byte
1703
1704
#define     gmd0_g0mr   g0mr_addr.bit.b0    /* (b1-b0) Communication mode select bit */
1705
#define     gmd1_g0mr   g0mr_addr.bit.b1
1706
#define     ckdir_g0mr  g0mr_addr.bit.b2    /* Internal/external clock select bit */
1707
                                            /* (b5-b3) Reserved bit (Set to 0) */
1708
#define     uform_g0mr  g0mr_addr.bit.b6    /* Transfer direction select bit */
1709
#define     irs_g0mr    g0mr_addr.bit.b7    /* Transmit interrupt cause select bit */
1710
1711
/*------------------------------------------------------
1712
    SI/O Communication Control Register 0
1713
------------------------------------------------------*/
1714
union byte_def g0cr_addr;
1715
#define     g0cr    g0cr_addr.byte
1716
1717
#define     ti_g0cr     g0cr_addr.bit.b0    /* Transmit buffer empty flag */
1718
#define     txept_g0cr  g0cr_addr.bit.b1    /* Transmit register empty flag */
1719
#define     ri_g0cr     g0cr_addr.bit.b2    /* Receive complete flag */
1720
                                            /* (b3) Nothing is assigned */
1721
#define     te_g0cr     g0cr_addr.bit.b4    /* Transmit enable bit */
1722
#define     re_g0cr     g0cr_addr.bit.b5    /* Receive enable bit */
1723
                                            /* (b7-b6) Reserved bit (Set to 0) */
1724
1725
/*------------------------------------------------------
1726
    SI/O Expansion Mode Register 0
1727
------------------------------------------------------*/
1728
union byte_def g0emr_addr;
1729
#define     g0emr       g0emr_addr.byte
1730
                                                /* (b0) Reserved bit (Set to 0) */
1731
#define     crcv_g0emr      g0emr_addr.bit.b1   /* CRC default value select bit */
1732
#define     acrc_g0emr      g0emr_addr.bit.b2   /* CRC reset select bit */
1733
#define     bsint_g0emr     g0emr_addr.bit.b3   /* Bit stuffing error interrupt select bit */
1734
#define     rxsl_g0emr      g0emr_addr.bit.b4   /* Receive source switch bit */
1735
#define     txsl_g0emr      g0emr_addr.bit.b5   /* Transmit source switch bit */
1736
#define     crc0_g0emr      g0emr_addr.bit.b6   /* CRC generation polynomial select bit */
1737
#define     crc1_g0emr      g0emr_addr.bit.b7   /* CRC generation polynomial select bit */
1738
1739
/*------------------------------------------------------
1740
    SI/O Expansion Transmit Control Register 0
1741
------------------------------------------------------*/
1742
union byte_def g0etc_addr;
1743
#define     g0etc       g0etc_addr.byte
1744
                                                /* (b2-b0) Reserved bit (Set to 0) */
1745
                                                /* (b3) Reserved bit (Set to 0) */
1746
#define     tcrce_g0etc     g0etc_addr.bit.b4   /* Transmit CRC enable bit */
1747
                                                /* (b5) Reserved bit (Set to 0) */
1748
#define     tbsf0_g0etc     g0etc_addr.bit.b6   /* Transmit bit stuffing "1" insert select bit */
1749
#define     tbsf1_g0etc     g0etc_addr.bit.b7   /* Transmit bit stuffing "0" insert select bit */
1750
1751
/*------------------------------------------------------
1752
    SI/O Expansion Receive Control Register 0
1753
------------------------------------------------------*/
1754
union byte_def g0erc_addr;
1755
#define     g0erc       g0erc_addr.byte
1756
#define     cmp0e_g0erc     g0erc_addr.bit.b0   /* Data compare function 0 select bit */
1757
#define     cmp1e_g0erc     g0erc_addr.bit.b1   /* Data compare function 1 select bit */
1758
#define     cmp2e_g0erc     g0erc_addr.bit.b2   /* Data compare function 2 select bit */
1759
#define     cmp3e_g0erc     g0erc_addr.bit.b3   /* Data compare function 3 select bit */
1760
#define     rcrce_g0erc     g0erc_addr.bit.b4   /* Receive CRC enable bit */
1761
#define     rshte_g0erc     g0erc_addr.bit.b5   /* Receive shift operation enable bit */
1762
#define     rbsf0_g0erc     g0erc_addr.bit.b6   /* Receive bit stuffing "1" delete select bit */
1763
#define     rbsf1_g0erc     g0erc_addr.bit.b7   /* Receive bit stuffing "0" delete select bit */
1764
1765
/*------------------------------------------------------
1766
    SI/O Special Communication Interrupt Detect Register 0
1767
------------------------------------------------------*/
1768
union byte_def g0irf_addr;
1769
#define     g0irf       g0irf_addr.byte
1770
                                                /* (b1-b0) Reserved bit (Set to 0) */
1771
#define     bserr_g0irf     g0irf_addr.bit.b2   /* Bit stuffing error detect flag */
1772
                                                /* (b3) Reserved bit (Set to 0) */
1773
#define     irf0_g0irf      g0irf_addr.bit.b4   /* Interrupt cause determination flag 0 */
1774
#define     irf1_g0irf      g0irf_addr.bit.b5   /* Interrupt cause determination flag 1 */
1775
#define     irf2_g0irf      g0irf_addr.bit.b6   /* Interrupt cause determination flag 2 */
1776
#define     irf3_g0irf      g0irf_addr.bit.b7   /* Interrupt cause determination flag 3 */
1777
1778
/*------------------------------------------------------
1779
    Receive Data Register 0
1780
------------------------------------------------------*/
1781
union byte_def g0dr_addr;
1782
#define     g0dr       g0dr_addr.byte
1783
1784
/*------------------------------------------------------
1785
    Transmit Buffer Register 0
1786
------------------------------------------------------*/
1787
union byte_def g0tb_addr;
1788
#define     g0tb       g0tb_addr.byte
1789
1790
/*------------------------------------------------------
1791
    Data Compare Register 00
1792
------------------------------------------------------*/
1793
union byte_def g0cmp0_addr;
1794
#define     g0cmp0       g0cmp0_addr.byte
1795
1796
/*------------------------------------------------------
1797
    Data Compare Register 01
1798
------------------------------------------------------*/
1799
union byte_def g0cmp1_addr;
1800
#define     g0cmp1       g0cmp1_addr.byte
1801
1802
/*------------------------------------------------------
1803
    Data Compare Register 02
1804
------------------------------------------------------*/
1805
union byte_def g0cmp2_addr;
1806
#define     g0cmp2       g0cmp2_addr.byte
1807
1808
/*------------------------------------------------------
1809
    Data Compare Register 03
1810
------------------------------------------------------*/
1811
union byte_def g0cmp3_addr;
1812
#define     g0cmp3       g0cmp3_addr.byte
1813
1814
/*------------------------------------------------------
1815
    Data Mask Register 00
1816
------------------------------------------------------*/
1817
union byte_def g0msk0_addr;
1818
#define     g0msk0       g0msk0_addr.byte
1819
1820
/*------------------------------------------------------
1821
    Data Mask Register 01
1822
------------------------------------------------------*/
1823
union byte_def g0msk1_addr;
1824
#define     g0msk1       g0msk1_addr.byte
1825
1826
/*------------------------------------------------------
1827
    Communication Clock Select Register
1828
------------------------------------------------------*/
1829
union byte_def ccs_addr;
1830
#define     ccs       ccs_addr.byte
1831
1832
#define     ccs0      ccs_addr.bit.b0   /* Communication unit 0 clock select bit */
1833
#define     ccs1      ccs_addr.bit.b1   /* Communication unit 0 clock select bit */
1834
#define     ccs2      ccs_addr.bit.b2   /* Communication unit 1 clock select bit */
1835
#define     ccs3      ccs_addr.bit.b3   /* Communication unit 1 clock select bit */
1836
                                        /* (b7-b4) Nothing is assigned */
1837
1838
/*------------------------------------------------------
1839
    Transmit Output Register 0
1840
------------------------------------------------------*/
1841
union byte_def g0to_addr;
1842
#define     g0to       g0to_addr.byte
1843
1844
/*------------------------------------------------------
1845
    Receive Input Register 0
1846
------------------------------------------------------*/
1847
union byte_def g0ri_addr;
1848
#define     g0ri       g0ri_addr.byte
1849
1850
/*------------------------------------------------------
1851
    Base Timer Control Register 10
1852
------------------------------------------------------*/
1853
union byte_def g1bcr0_addr;
1854
#define     g1bcr0       g1bcr0_addr.byte
1855
#define     bck0_g1bcr0        g1bcr0_addr.bit.b0   /* (b1-b0) Count source select bit */
1856
#define     bck1_g1bcr0        g1bcr0_addr.bit.b1
1857
#define     div0_g1bcr0        g1bcr0_addr.bit.b2   /* (b6-b2) Count source division ratio select bit */
1858
#define     div1_g1bcr0        g1bcr0_addr.bit.b3
1859
#define     div2_g1bcr0        g1bcr0_addr.bit.b4
1860
#define     div3_g1bcr0        g1bcr0_addr.bit.b5
1861
#define     div4_g1bcr0        g1bcr0_addr.bit.b6
1862
#define     it_g1bcr0          g1bcr0_addr.bit.b7   /* Base timer interrupt select bit */
1863
1864
/*------------------------------------------------------
1865
    Base Timer Control Register 11
1866
------------------------------------------------------*/
1867
union byte_def g1bcr1_addr;
1868
#define     g1bcr1       g1bcr1_addr.byte
1869
                                                    /* (b0) Nothing is assigned */
1870
#define     rst1_g1bcr1        g1bcr1_addr.bit.b1   /* Base timer reset cause select bit 1 */
1871
#define     rst2_g1bcr1        g1bcr1_addr.bit.b2   /* Base timer reset cause select bit 2 */
1872
                                                    /* (b3) Reserved bit (Set to 0) */
1873
#define     bts_g1bcr1         g1bcr1_addr.bit.b4   /* Base timer start bit */
1874
#define     ud0_g1bcr1         g1bcr1_addr.bit.b5   /* (b6-b5) Counter increment/decrement control bit */
1875
#define     ud1_g1bcr1         g1bcr1_addr.bit.b6
1876
                                                    /* (b7) Nothing is assigned */
1877
1878
/*------------------------------------------------------
1879
    Time Measurement Control Register 10
1880
------------------------------------------------------*/
1881
union byte_def g1tmcr0_addr;
1882
#define     g1tmcr0       g1tmcr0_addr.byte
1883
#define     cts0_g1tmcr0      g1tmcr0_addr.bit.b0   /* (b1b0) Time measurement trigger select bit */
1884
#define     cts1_g1tmcr0      g1tmcr0_addr.bit.b1
1885
#define     df0_g1tmcr0       g1tmcr0_addr.bit.b2   /* (b3b2) Digital filter function select bit */
1886
#define     df1_g1tmcr0       g1tmcr0_addr.bit.b3
1887
#define     gt_g1tmcr0        g1tmcr0_addr.bit.b4   /* Gate function select bit */
1888
#define     goc_g1tmcr0       g1tmcr0_addr.bit.b5   /* Gate function clear select bit */
1889
#define     gsc_g1tmcr0       g1tmcr0_addr.bit.b6   /* Gate function clear bit */
1890
#define     pr_g1tmcr0        g1tmcr0_addr.bit.b7   /* Prescaler function select bit */
1891
1892
/*------------------------------------------------------
1893
    Time Measurement Control Register 11
1894
------------------------------------------------------*/
1895
union byte_def g1tmcr1_addr;
1896
#define     g1tmcr1       g1tmcr1_addr.byte
1897
#define     cts0_g1tmcr1      g1tmcr1_addr.bit.b0
1898
#define     cts1_g1tmcr1      g1tmcr1_addr.bit.b1
1899
#define     df0_g1tmcr1       g1tmcr1_addr.bit.b2
1900
#define     df1_g1tmcr1       g1tmcr1_addr.bit.b3
1901
#define     gt_g1tmcr1        g1tmcr1_addr.bit.b4
1902
#define     goc_g1tmcr1       g1tmcr1_addr.bit.b5
1903
#define     gsc_g1tmcr1       g1tmcr1_addr.bit.b6
1904
#define     pr_g1tmcr1        g1tmcr1_addr.bit.b7
1905
1906
/*------------------------------------------------------
1907
    Time Measurement Control Register 12
1908
------------------------------------------------------*/
1909
union byte_def g1tmcr2_addr;
1910
#define     g1tmcr2       g1tmcr2_addr.byte
1911
#define     cts0_g1tmcr2      g1tmcr2_addr.bit.b0
1912
#define     cts1_g1tmcr2      g1tmcr2_addr.bit.b1
1913
#define     df0_g1tmcr2       g1tmcr2_addr.bit.b2
1914
#define     df1_g1tmcr2       g1tmcr2_addr.bit.b3
1915
#define     gt_g1tmcr2        g1tmcr2_addr.bit.b4
1916
#define     goc_g1tmcr2       g1tmcr2_addr.bit.b5
1917
#define     gsc_g1tmcr2       g1tmcr2_addr.bit.b6
1918
#define     pr_g1tmcr2        g1tmcr2_addr.bit.b7
1919
1920
/*------------------------------------------------------
1921
    Time Measurement Control Register 13
1922
------------------------------------------------------*/
1923
union byte_def g1tmcr3_addr;
1924
#define     g1tmcr3       g1tmcr3_addr.byte
1925
#define     cts0_g1tmcr3      g1tmcr3_addr.bit.b0
1926
#define     cts1_g1tmcr3      g1tmcr3_addr.bit.b1
1927
#define     df0_g1tmcr3       g1tmcr3_addr.bit.b2
1928
#define     df1_g1tmcr3       g1tmcr3_addr.bit.b3
1929
#define     gt_g1tmcr3        g1tmcr3_addr.bit.b4
1930
#define     goc_g1tmcr3       g1tmcr3_addr.bit.b5
1931
#define     gsc_g1tmcr3       g1tmcr3_addr.bit.b6
1932
#define     pr_g1tmcr3        g1tmcr3_addr.bit.b7
1933
1934
/*------------------------------------------------------
1935
    Time Measurement Control Register 14
1936
------------------------------------------------------*/
1937
union byte_def g1tmcr4_addr;
1938
#define     g1tmcr4       g1tmcr4_addr.byte
1939
#define     cts0_g1tmcr4      g1tmcr4_addr.bit.b0
1940
#define     cts1_g1tmcr4      g1tmcr4_addr.bit.b1
1941
#define     df0_g1tmcr4       g1tmcr4_addr.bit.b2
1942
#define     df1_g1tmcr4       g1tmcr4_addr.bit.b3
1943
#define     gt_g1tmcr4        g1tmcr4_addr.bit.b4
1944
#define     goc_g1tmcr4       g1tmcr4_addr.bit.b5
1945
#define     gsc_g1tmcr4       g1tmcr4_addr.bit.b6
1946
#define     pr_g1tmcr4        g1tmcr4_addr.bit.b7
1947
1948
/*------------------------------------------------------
1949
    Time Measurement Control Register 15
1950
------------------------------------------------------*/
1951
union byte_def g1tmcr5_addr;
1952
#define     g1tmcr5       g1tmcr5_addr.byte
1953
#define     cts0_g1tmcr5      g1tmcr5_addr.bit.b0
1954
#define     cts1_g1tmcr5      g1tmcr5_addr.bit.b1
1955
#define     df0_g1tmcr5       g1tmcr5_addr.bit.b2
1956
#define     df1_g1tmcr5       g1tmcr5_addr.bit.b3
1957
#define     gt_g1tmcr5        g1tmcr5_addr.bit.b4
1958
#define     goc_g1tmcr5       g1tmcr5_addr.bit.b5
1959
#define     gsc_g1tmcr5       g1tmcr5_addr.bit.b6
1960
#define     pr_g1tmcr5        g1tmcr5_addr.bit.b7
1961
1962
/*------------------------------------------------------
1963
    Time Measurement Control Register 16
1964
------------------------------------------------------*/
1965
union byte_def g1tmcr6_addr;
1966
#define     g1tmcr6       g1tmcr6_addr.byte
1967
#define     cts0_g1tmcr6      g1tmcr6_addr.bit.b0
1968
#define     cts1_g1tmcr6      g1tmcr6_addr.bit.b1
1969
#define     df0_g1tmcr6       g1tmcr6_addr.bit.b2
1970
#define     df1_g1tmcr6       g1tmcr6_addr.bit.b3
1971
#define     gt_g1tmcr6        g1tmcr6_addr.bit.b4
1972
#define     goc_g1tmcr6       g1tmcr6_addr.bit.b5
1973
#define     gsc_g1tmcr6       g1tmcr6_addr.bit.b6
1974
#define     pr_g1tmcr6        g1tmcr6_addr.bit.b7
1975
1976
/*------------------------------------------------------
1977
    Time Measurement Control Register 17
1978
------------------------------------------------------*/
1979
union byte_def g1tmcr7_addr;
1980
#define     g1tmcr7       g1tmcr7_addr.byte
1981
#define     cts0_g1tmcr7      g1tmcr7_addr.bit.b0
1982
#define     cts1_g1tmcr7      g1tmcr7_addr.bit.b1
1983
#define     df0_g1tmcr7       g1tmcr7_addr.bit.b2
1984
#define     df1_g1tmcr7       g1tmcr7_addr.bit.b3
1985
#define     gt_g1tmcr7        g1tmcr7_addr.bit.b4
1986
#define     goc_g1tmcr7       g1tmcr7_addr.bit.b5
1987
#define     gsc_g1tmcr7       g1tmcr7_addr.bit.b6
1988
#define     pr_g1tmcr7        g1tmcr7_addr.bit.b7
1989
1990
/*------------------------------------------------------
1991
    Time Measurement Prescaler Register 16
1992
------------------------------------------------------*/
1993
union byte_def g1tpr6_addr;
1994
#define     g1tpr6       g1tpr6_addr.byte
1995
1996
/*------------------------------------------------------
1997
    Time Measurement Prescaler Register 17
1998
------------------------------------------------------*/
1999
union byte_def g1tpr7_addr;
2000
#define     g1tpr7       g1tpr7_addr.byte
2001
2002
/*------------------------------------------------------
2003
    Waveform Generation Control Register 10
2004
------------------------------------------------------*/
2005
union byte_def g1pocr0_addr;
2006
#define     g1pocr0       g1pocr0_addr.byte
2007
#define     mod0_g1pocr0        g1pocr0_addr.bit.b0     /* (b2-b0) Operation mode select bit */
2008
#define     mod1_g1pocr0        g1pocr0_addr.bit.b1
2009
#define     mod2_g1pocr0        g1pocr0_addr.bit.b2
2010
                                                        /* (b3) Nothing is assigned */
2011
#define     ivl_g1pocr0         g1pocr0_addr.bit.b4     /* Output initial value select bit */
2012
#define     rld_g1pocr0         g1pocr0_addr.bit.b5     /* G1POj register value reload timing select bit */
2013
#define     btre_g1pocr0        g1pocr0_addr.bit.b6     /* Base timer reset enable bit */
2014
#define     inv_g1pocr0         g1pocr0_addr.bit.b7     /* Inverse output function select bit */
2015
2016
/*------------------------------------------------------
2017
     Waveform Generation Control Register 11
2018
------------------------------------------------------*/
2019
union byte_def g1pocr1_addr;
2020
#define     g1pocr1       g1pocr1_addr.byte
2021
#define     mod0_g1pocr1        g1pocr1_addr.bit.b0
2022
#define     mod1_g1pocr1        g1pocr1_addr.bit.b1
2023
#define     mod2_g1pocr1        g1pocr1_addr.bit.b2
2024
2025
#define     ivl_g1pocr1         g1pocr1_addr.bit.b4
2026
#define     rld_g1pocr1         g1pocr1_addr.bit.b5
2027
#define     btre_g1pocr1        g1pocr1_addr.bit.b6
2028
#define     inv_g1pocr1         g1pocr1_addr.bit.b7
2029
2030
/*------------------------------------------------------
2031
     Waveform Generation Control Register 12
2032
------------------------------------------------------*/
2033
union byte_def g1pocr2_addr;
2034
#define     g1pocr2       g1pocr2_addr.byte
2035
#define     mod0_g1pocr2        g1pocr2_addr.bit.b0
2036
#define     mod1_g1pocr2        g1pocr2_addr.bit.b1
2037
#define     mod2_g1pocr2        g1pocr2_addr.bit.b2
2038
2039
#define     ivl_g1pocr2         g1pocr2_addr.bit.b4
2040
#define     rld_g1pocr2         g1pocr2_addr.bit.b5
2041
#define     btre_g1pocr2        g1pocr2_addr.bit.b6
2042
#define     inv_g1pocr2         g1pocr2_addr.bit.b7
2043
2044
/*------------------------------------------------------
2045
     Waveform Generation Control Register 13
2046
------------------------------------------------------*/
2047
union byte_def g1pocr3_addr;
2048
#define     g1pocr3       g1pocr3_addr.byte
2049
#define     mod0_g1pocr3        g1pocr3_addr.bit.b0
2050
#define     mod1_g1pocr3        g1pocr3_addr.bit.b1
2051
#define     mod2_g1pocr3        g1pocr3_addr.bit.b2
2052
2053
#define     ivl_g1pocr3         g1pocr3_addr.bit.b4
2054
#define     rld_g1pocr3         g1pocr3_addr.bit.b5
2055
#define     btre_g1pocr3        g1pocr3_addr.bit.b6
2056
#define     inv_g1pocr3         g1pocr3_addr.bit.b7
2057
2058
/*------------------------------------------------------
2059
     Waveform Generation Control Register 14
2060
------------------------------------------------------*/
2061
union byte_def g1pocr4_addr;
2062
#define     g1pocr4       g1pocr4_addr.byte
2063
#define     mod0_g1pocr4        g1pocr4_addr.bit.b0
2064
#define     mod1_g1pocr4        g1pocr4_addr.bit.b1
2065
#define     mod2_g1pocr4        g1pocr4_addr.bit.b2
2066
2067
#define     ivl_g1pocr4         g1pocr4_addr.bit.b4
2068
#define     rld_g1pocr4         g1pocr4_addr.bit.b5
2069
#define     btre_g1pocr4        g1pocr4_addr.bit.b6
2070
#define     inv_g1pocr4         g1pocr4_addr.bit.b7
2071
2072
/*------------------------------------------------------
2073
     Waveform Generation Control Register 15
2074
------------------------------------------------------*/
2075
union byte_def g1pocr5_addr;
2076
#define     g1pocr5       g1pocr5_addr.byte
2077
#define     mod0_g1pocr5        g1pocr5_addr.bit.b0
2078
#define     mod1_g1pocr5        g1pocr5_addr.bit.b1
2079
#define     mod2_g1pocr5        g1pocr5_addr.bit.b2
2080
2081
#define     ivl_g1pocr5         g1pocr5_addr.bit.b4
2082
#define     rld_g1pocr5         g1pocr5_addr.bit.b5
2083
#define     btre_g1pocr5        g1pocr5_addr.bit.b6
2084
#define     inv_g1pocr5         g1pocr5_addr.bit.b7
2085
2086
/*------------------------------------------------------
2087
     Waveform Generation Control Register 16
2088
------------------------------------------------------*/
2089
union byte_def g1pocr6_addr;
2090
#define     g1pocr6       g1pocr6_addr.byte
2091
#define     mod0_g1pocr6        g1pocr6_addr.bit.b0
2092
#define     mod1_g1pocr6        g1pocr6_addr.bit.b1
2093
#define     mod2_g1pocr6        g1pocr6_addr.bit.b2
2094
2095
#define     ivl_g1pocr6         g1pocr6_addr.bit.b4
2096
#define     rld_g1pocr6         g1pocr6_addr.bit.b5
2097
#define     btre_g1pocr6        g1pocr6_addr.bit.b6
2098
#define     inv_g1pocr6         g1pocr6_addr.bit.b7
2099
2100
/*------------------------------------------------------
2101
     Waveform Generation Control Register 17
2102
------------------------------------------------------*/
2103
union byte_def g1pocr7_addr;
2104
#define     g1pocr7       g1pocr7_addr.byte
2105
#define     mod0_g1pocr7        g1pocr7_addr.bit.b0
2106
#define     mod1_g1pocr7        g1pocr7_addr.bit.b1
2107
#define     mod2_g1pocr7        g1pocr7_addr.bit.b2
2108
2109
#define     ivl_g1pocr7         g1pocr7_addr.bit.b4
2110
#define     rld_g1pocr7         g1pocr7_addr.bit.b5
2111
#define     btre_g1pocr7        g1pocr7_addr.bit.b6
2112
#define     inv_g1pocr7         g1pocr7_addr.bit.b7
2113
2114
/*------------------------------------------------------
2115
    Waveform Generation Control Register 20
2116
------------------------------------------------------*/
2117
union byte_def g2pocr0_addr;
2118
#define     g2pocr0       g2pocr0_addr.byte
2119
#define     mod0_g2pocr0        g2pocr0_addr.bit.b0     /* (b2-b0) Operation mode select bit */
2120
#define     mod1_g2pocr0        g2pocr0_addr.bit.b1
2121
#define     mod2_g2pocr0        g2pocr0_addr.bit.b2
2122
                                                        /* (b3) Nothing is assigned */
2123
#define     ivl_g2pocr0         g2pocr0_addr.bit.b4     /* Output initial value select bit */
2124
#define     rld_g2pocr0         g2pocr0_addr.bit.b5     /* G2POj register value reload timing select bit */
2125
#define     btre_g2pocr0        g2pocr0_addr.bit.b6     /* Base timer reset enable bit */
2126
#define     inv_g2pocr0         g2pocr0_addr.bit.b7     /* Inverse output function select bit */
2127
2128
/*------------------------------------------------------
2129
     Waveform Generation Control Register 21
2130
------------------------------------------------------*/
2131
union byte_def g2pocr1_addr;
2132
#define     g2pocr1       g2pocr1_addr.byte
2133
#define     mod0_g2pocr1        g2pocr1_addr.bit.b0
2134
#define     mod1_g2pocr1        g2pocr1_addr.bit.b1
2135
#define     mod2_g2pocr1        g2pocr1_addr.bit.b2
2136
2137
#define     ivl_g2pocr1         g2pocr1_addr.bit.b4
2138
#define     rld_g2pocr1         g2pocr1_addr.bit.b5
2139
#define     btre_g2pocr1        g2pocr1_addr.bit.b6
2140
#define     inv_g2pocr1         g2pocr1_addr.bit.b7
2141
2142
/*------------------------------------------------------
2143
     Waveform Generation Control Register 22
2144
------------------------------------------------------*/
2145
union byte_def g2pocr2_addr;
2146
#define     g2pocr2       g2pocr2_addr.byte
2147
#define     mod0_g2pocr2        g2pocr2_addr.bit.b0
2148
#define     mod1_g2pocr2        g2pocr2_addr.bit.b1
2149
#define     mod2_g2pocr2        g2pocr2_addr.bit.b2
2150
2151
#define     ivl_g2pocr2         g2pocr2_addr.bit.b4
2152
#define     rld_g2pocr2         g2pocr2_addr.bit.b5
2153
#define     btre_g2pocr2        g2pocr2_addr.bit.b6
2154
#define     inv_g2pocr2         g2pocr2_addr.bit.b7
2155
2156
/*------------------------------------------------------
2157
     Waveform Generation Control Register 23
2158
------------------------------------------------------*/
2159
union byte_def g2pocr3_addr;
2160
#define     g2pocr3       g2pocr3_addr.byte
2161
#define     mod0_g2pocr3        g2pocr3_addr.bit.b0
2162
#define     mod1_g2pocr3        g2pocr3_addr.bit.b1
2163
#define     mod2_g2pocr3        g2pocr3_addr.bit.b2
2164
2165
#define     ivl_g2pocr3         g2pocr3_addr.bit.b4
2166
#define     rld_g2pocr3         g2pocr3_addr.bit.b5
2167
#define     btre_g2pocr3        g2pocr3_addr.bit.b6
2168
#define     inv_g2pocr3         g2pocr3_addr.bit.b7
2169
2170
/*------------------------------------------------------
2171
     Waveform Generation Control Register 24
2172
------------------------------------------------------*/
2173
union byte_def g2pocr4_addr;
2174
#define     g2pocr4       g2pocr4_addr.byte
2175
#define     mod0_g2pocr4        g2pocr4_addr.bit.b0
2176
#define     mod1_g2pocr4        g2pocr4_addr.bit.b1
2177
#define     mod2_g2pocr4        g2pocr4_addr.bit.b2
2178
2179
#define     ivl_g2pocr4         g2pocr4_addr.bit.b4
2180
#define     rld_g2pocr4         g2pocr4_addr.bit.b5
2181
#define     btre_g2pocr4        g2pocr4_addr.bit.b6
2182
#define     inv_g2pocr4         g2pocr4_addr.bit.b7
2183
2184
/*------------------------------------------------------
2185
     Waveform Generation Control Register 25
2186
------------------------------------------------------*/
2187
union byte_def g2pocr5_addr;
2188
#define     g2pocr5       g2pocr5_addr.byte
2189
#define     mod0_g2pocr5        g2pocr5_addr.bit.b0
2190
#define     mod1_g2pocr5        g2pocr5_addr.bit.b1
2191
#define     mod2_g2pocr5        g2pocr5_addr.bit.b2
2192
2193
#define     ivl_g2pocr5         g2pocr5_addr.bit.b4
2194
#define     rld_g2pocr5         g2pocr5_addr.bit.b5
2195
#define     btre_g2pocr5        g2pocr5_addr.bit.b6
2196
#define     inv_g2pocr5         g2pocr5_addr.bit.b7
2197
2198
/*------------------------------------------------------
2199
     Waveform Generation Control Register 26
2200
------------------------------------------------------*/
2201
union byte_def g2pocr6_addr;
2202
#define     g2pocr6       g2pocr6_addr.byte
2203
#define     mod0_g2pocr6        g2pocr6_addr.bit.b0
2204
#define     mod1_g2pocr6        g2pocr6_addr.bit.b1
2205
#define     mod2_g2pocr6        g2pocr6_addr.bit.b2
2206
2207
#define     ivl_g2pocr6         g2pocr6_addr.bit.b4
2208
#define     rld_g2pocr6         g2pocr6_addr.bit.b5
2209
#define     btre_g2pocr6        g2pocr6_addr.bit.b6
2210
#define     inv_g2pocr6         g2pocr6_addr.bit.b7
2211
2212
/*------------------------------------------------------
2213
     Waveform Generation Control Register 27
2214
------------------------------------------------------*/
2215
union byte_def g2pocr7_addr;
2216
#define     g2pocr7       g2pocr7_addr.byte
2217
#define     mod0_g2pocr7        g2pocr7_addr.bit.b0
2218
#define     mod1_g2pocr7        g2pocr7_addr.bit.b1
2219
#define     mod2_g2pocr7        g2pocr7_addr.bit.b2
2220
2221
#define     ivl_g2pocr7         g2pocr7_addr.bit.b4
2222
#define     rld_g2pocr7         g2pocr7_addr.bit.b5
2223
#define     btre_g2pocr7        g2pocr7_addr.bit.b6
2224
#define     inv_g2pocr7         g2pocr7_addr.bit.b7
2225
2226
/*------------------------------------------------------
2227
    Base Timer Control Register 20
2228
------------------------------------------------------*/
2229
union byte_def g2bcr0_addr;
2230
#define     g2bcr0       g2bcr0_addr.byte
2231
#define     bck0_g2bcr0        g2bcr0_addr.bit.b0   /* (b1-b0) Count source select bit */
2232
#define     bck1_g2bcr0        g2bcr0_addr.bit.b1
2233
#define     div0_g2bcr0        g2bcr0_addr.bit.b2   /* (b6-b2) Count source division ratio select bit */
2234
#define     div1_g2bcr0        g2bcr0_addr.bit.b3
2235
#define     div2_g2bcr0        g2bcr0_addr.bit.b4
2236
#define     div3_g2bcr0        g2bcr0_addr.bit.b5
2237
#define     div4_g2bcr0        g2bcr0_addr.bit.b6
2238
#define     it_g2bcr0          g2bcr0_addr.bit.b7   /* Base timer interrupt select bit */
2239
2240
/*------------------------------------------------------
2241
    Base Timer Control Register 21
2242
------------------------------------------------------*/
2243
union byte_def g2bcr1_addr;
2244
#define     g2bcr1       g2bcr1_addr.byte
2245
                                                    /* (b0) Nothing is assigned */
2246
#define     rst1_g2bcr1        g2bcr1_addr.bit.b1   /* Base timer reset cause select bit 1 */
2247
#define     rst2_g2bcr1        g2bcr1_addr.bit.b2   /* Base timer reset cause select bit 2 */
2248
                                                    /* (b3) Reserved bit (Set to 0) */
2249
#define     bts_g2bcr1         g2bcr1_addr.bit.b4   /* Base timer start bit */
2250
#define     ud0_g2bcr1         g2bcr1_addr.bit.b5   /* (b6-b5) Counter increment/decrement control bit */
2251
#define     ud1_g2bcr1         g2bcr1_addr.bit.b6
2252
                                                    /* (b7) Nothing is assigned */
2253
2254
/*------------------------------------------------------
2255
    Base Timer Start Register
2256
------------------------------------------------------*/
2257
union byte_def btsr_addr;
2258
#define     btsr         btsr_addr.byte
2259
                                                    /* (b0) Reserved bit (Set to 0) */
2260
#define     bt1s               btsr_addr.bit.b1
2261
#define     bt2s               btsr_addr.bit.b2
2262
                                                    /* (b3) Reserved bit (Set to 0) */
2263
                                                    /* (b7-b4) Nothing is assigned */
2264
/*------------------------------------------------------
2265

2266
------------------------------------------------------*/
2267
union byte_def iecr_addr;
2268
#define     iecr         iecr_addr.byte
2269
2270
#define     ieb                iecr_addr.bit.b0
2271
#define     iets               iecr_addr.bit.b1
2272
#define     iebbs              iecr_addr.bit.b2
2273
                                                    /* (b5-b3) Nothing is assigned */
2274
#define     df                 iecr_addr.bit.b6
2275
#define     iem                iecr_addr.bit.b7
2276
2277
/*------------------------------------------------------
2278

2279
------------------------------------------------------*/
2280
union byte_def ietif_addr;
2281
#define     ietif        ietif_addr.byte
2282
2283
#define     ietnf_ietif        ietif_addr.bit.b0
2284
#define     ieack_ietif        ietif_addr.bit.b1
2285
#define     ietmb_ietif        ietif_addr.bit.b2
2286
#define     iett_ietif         ietif_addr.bit.b3
2287
#define     ieabl_ietif        ietif_addr.bit.b4
2288
                                                    /* (b7-b5) Nothing is assigned */
2289
2290
/*------------------------------------------------------
2291

2292
------------------------------------------------------*/
2293
union byte_def ierif_addr;
2294
#define     ierif        ierif_addr.byte
2295
2296
#define     ietnf_ierif        ierif_addr.bit.b0
2297
#define     iepcr_ierif        ierif_addr.bit.b1
2298
#define     iermb_ierif        ierif_addr.bit.b2
2299
#define     iert_ierif         ierif_addr.bit.b3
2300
#define     ieretc_ierif       ierif_addr.bit.b4
2301
                                                    /* (b7-b5) Nothing is assigned */
2302
2303
/*------------------------------------------------------
2304
    SI/O Communication Mode Register 2
2305
------------------------------------------------------*/
2306
union byte_def g2mr_addr;
2307
#define     g2mr       g2mr_addr.byte
2308
#define     gmd0_g2mr    g2mr_addr.bit.b0   /* (b1-b0) Communication mode select bit */
2309
#define     gmd1_g2mr    g2mr_addr.bit.b1
2310
#define     ckdir_g2mr   g2mr_addr.bit.b2   /* Internal/external clock select bit */
2311
                                                    /* (b5-b3) Nothing is assigned */
2312
#define     uform_g2mr   g2mr_addr.bit.b6   /* Transfer direction select bit */
2313
#define     irs_g2mr     g2mr_addr.bit.b7   /* Transmit interrupt cause select bit */
2314
2315
/*------------------------------------------------------
2316
    SI/O Communication Control Register 2
2317
------------------------------------------------------*/
2318
union byte_def g2cr_addr;
2319
#define     g2cr       g2cr_addr.byte
2320
#define     te_g2cr             g2cr_addr.bit.b0    /* Transmit enable bit */
2321
#define     txept_g2cr          g2cr_addr.bit.b1    /* Transmit register empty flag */
2322
#define     ti_g2cr             g2cr_addr.bit.b2    /* Transmit buffer empty flag */
2323
                                                    /* (b3) Nothing is assigned */
2324
#define     re_g2cr             g2cr_addr.bit.b4    /* Receive enable bit */
2325
#define     ri_g2cr             g2cr_addr.bit.b5    /* Receive complete flag */
2326
#define     opol_g2cr           g2cr_addr.bit.b6    /* ISRxD input polarity switch bit */
2327
#define     ipol_g2cr           g2cr_addr.bit.b7    /* ISTxD output polarity switch bit */
2328
2329
/*------------------------------------------------------
2330
    Function Enable Register 2
2331
------------------------------------------------------*/
2332
union byte_def g2fe_addr;
2333
#define     g2fe       g2fe_addr.byte
2334
#define     ife0_g2fe    g2fe_addr.bit.b0   /* Channel 0 function enable bit */
2335
#define     ife1_g2fe    g2fe_addr.bit.b1   /* Channel 1 function enable bit */
2336
#define     ife2_g2fe    g2fe_addr.bit.b2   /* Channel 2 function enable bit */
2337
#define     ife3_g2fe    g2fe_addr.bit.b3   /* Channel 3 function enable bit */
2338
#define     ife4_g2fe    g2fe_addr.bit.b4   /* Channel 4 function enable bit */
2339
#define     ife5_g2fe    g2fe_addr.bit.b5   /* Channel 5 function enable bit */
2340
#define     ife6_g2fe    g2fe_addr.bit.b6   /* Channel 6 function enable bit */
2341
#define     ife7_g2fe    g2fe_addr.bit.b7   /* Channel 7 function enable bit */
2342
2343
/*------------------------------------------------------
2344

2345
------------------------------------------------------*/
2346
union byte_def g2rtp_addr;
2347
#define     g2rtp      g2rtp_addr.byte
2348
#define     rtp0_g2rtp   g2rtp_addr.bit.b0
2349
#define     rtp1_g2rtp   g2rtp_addr.bit.b1
2350
#define     rtp2_g2rtp   g2rtp_addr.bit.b2
2351
#define     rtp3_g2rtp   g2rtp_addr.bit.b3
2352
#define     rtp4_g2rtp   g2rtp_addr.bit.b4
2353
#define     rtp5_g2rtp   g2rtp_addr.bit.b5
2354
#define     rtp6_g2rtp   g2rtp_addr.bit.b6
2355
#define     rtp7_g2rtp   g2rtp_addr.bit.b7
2356
2357
/*------------------------------------------------------
2358
    Function Select Register 1
2359
------------------------------------------------------*/
2360
union byte_def g1fs_addr;
2361
#define     g1fs       g1fs_addr.byte
2362
#define     fsc0_g1fs    g1fs_addr.bit.b0   /* Channel 0 time measurement/waveform generation function select bit */
2363
#define     fsc1_g1fs    g1fs_addr.bit.b1   /* Channel 1 time measurement/waveform generation function select bit */
2364
#define     fsc2_g1fs    g1fs_addr.bit.b2   /* Channel 2 time measurement/waveform generation function select bit */
2365
#define     fsc3_g1fs    g1fs_addr.bit.b3   /* Channel 3 time measurement/waveform generation function select bit */
2366
#define     fsc4_g1fs    g1fs_addr.bit.b4   /* Channel 4 time measurement/waveform generation function select bit */
2367
#define     fsc5_g1fs    g1fs_addr.bit.b5   /* Channel 5 time measurement/waveform generation function select bit */
2368
#define     fsc6_g1fs    g1fs_addr.bit.b6   /* Channel 6 time measurement/waveform generation function select bit */
2369
#define     fsc7_g1fs    g1fs_addr.bit.b7   /* Channel 7 time measurement/waveform generation function select bit */
2370
2371
/*------------------------------------------------------
2372
    Function Enable Register 1
2373
------------------------------------------------------*/
2374
union byte_def g1fe_addr;
2375
#define     g1fe       g1fe_addr.byte
2376
#define     ife0_g1fe    g1fe_addr.bit.b0   /* Channel 0 function enable bit */
2377
#define     ife1_g1fe    g1fe_addr.bit.b1   /* Channel 1 function enable bit */
2378
#define     ife2_g1fe    g1fe_addr.bit.b2   /* Channel 2 function enable bit */
2379
#define     ife3_g1fe    g1fe_addr.bit.b3   /* Channel 3 function enable bit */
2380
#define     ife4_g1fe    g1fe_addr.bit.b4   /* Channel 4 function enable bit */
2381
#define     ife5_g1fe    g1fe_addr.bit.b5   /* Channel 5 function enable bit */
2382
#define     ife6_g1fe    g1fe_addr.bit.b6   /* Channel 6 function enable bit */
2383
#define     ife7_g1fe    g1fe_addr.bit.b7   /* Channel 7 function enable bit */
2384
2385
/*------------------------------------------------------
2386
    SI/O Communication Mode Register 1
2387
------------------------------------------------------*/
2388
union byte_def g1mr_addr;
2389
#define     g1mr       g1mr_addr.byte
2390
#define     gmd0_g1mr    g1mr_addr.bit.b0   /* (b1-b0) Communication mode select bit */
2391
#define     gmd1_g1mr    g1mr_addr.bit.b1
2392
#define     ckdir_g1mr   g1mr_addr.bit.b2   /* Internal/external clock select bit */
2393
#define     stps_g1mr    g1mr_addr.bit.b3   /* Stop bit length select bit */
2394
#define     pry_g1mr     g1mr_addr.bit.b4   /* Odd/Even parity select bit */
2395
#define     prye_g1mr    g1mr_addr.bit.b5   /* Parity enable bit */
2396
#define     uform_g1mr   g1mr_addr.bit.b6   /* Transfer direction select bit */
2397
#define     irs_g1mr     g1mr_addr.bit.b7   /* Transmit interrupt cause select bit */
2398
2399
/*------------------------------------------------------
2400
    SI/O Communication Control Register 1
2401
------------------------------------------------------*/
2402
union byte_def g1cr_addr;
2403
#define     g1cr       g1cr_addr.byte
2404
#define     ti_g1cr             g1cr_addr.bit.b0    /* Transmit buffer empty flag */
2405
#define     txept_g1cr          g1cr_addr.bit.b1    /* Transmit register empty flag */
2406
#define     ri_g1cr             g1cr_addr.bit.b2    /* Receive complete flag */
2407
                                                    /* (b3) Nothing is assigned */
2408
#define     te_g1cr             g1cr_addr.bit.b4    /* Transmit enable bit */
2409
#define     re_g1cr             g1cr_addr.bit.b5    /* Receive enable bit */
2410
#define     ipol_g1cr           g1cr_addr.bit.b6    /* ISRxD input polarity switch bit */
2411
#define     opol_g1cr           g1cr_addr.bit.b7    /* ISTxD output polarity switch bit */
2412
2413
/*------------------------------------------------------
2414
    SI/O Expansion Mode Register 1
2415
------------------------------------------------------*/
2416
union byte_def g1emr_addr;
2417
#define     g1emr       g1emr_addr.byte
2418
#define     smode_g1emr         g1emr_addr.bit.b0   /* Synchronouse mode select bit */
2419
#define     crcv_g1emr          g1emr_addr.bit.b1   /* CRC initial value select bit */
2420
#define     acrc_g1emr          g1emr_addr.bit.b2   /* CRC initialization select bit */
2421
#define     bsint_g1emr         g1emr_addr.bit.b3   /* Bit stuffing error interrupt select bit */
2422
#define     rxsl_g1emr          g1emr_addr.bit.b4   /* Receive source switch bit */
2423
#define     txsl_g1emr          g1emr_addr.bit.b5   /* Transmit source switch bit */
2424
#define     crc0_g1emr          g1emr_addr.bit.b6   /* CRC generation polynomial select bit */
2425
#define     crc1_g1emr          g1emr_addr.bit.b7   /* CRC generation polynomial select bit */
2426
2427
/*------------------------------------------------------
2428
    SI/O Expansion Transmit Control Register 1
2429
------------------------------------------------------*/
2430
union byte_def g1etc_addr;
2431
#define     g1etc       g1etc_addr.byte
2432
                                                    /* (b2-b0) Reserved bit (Set to 0) */
2433
#define     sof_g1etc         g1etc_addr.bit.b3     /* SOF transmit request bit */
2434
#define     tcrce_g1etc       g1etc_addr.bit.b4     /* Transmit CRC enable bit */
2435
#define     abte_g1etc        g1etc_addr.bit.b5     /* Arbitration enable bit */
2436
#define     tbsf0_g1etc       g1etc_addr.bit.b6     /* Transmit bit stuffing "1" insert select bit */
2437
#define     tbsf1_g1etc       g1etc_addr.bit.b7     /* Transmit bit stuffing "0" insert select bit */
2438
2439
/*------------------------------------------------------
2440
    SI/O Expansion Receive Control Register 1
2441
------------------------------------------------------*/
2442
union byte_def g1erc_addr;
2443
#define     g1erc       g1erc_addr.byte
2444
#define     cmp0e_g1erc       g1erc_addr.bit.b0     /* Data compare function 0 select bit */
2445
#define     cmp1e_g1erc       g1erc_addr.bit.b1     /* Data compare function 1 select bit */
2446
#define     cmp2e_g1erc       g1erc_addr.bit.b2     /* Data compare function 2 select bit */
2447
#define     cmp3e_g1erc       g1erc_addr.bit.b3     /* Data compare function 3 select bit */
2448
#define     rcrce_g1erc       g1erc_addr.bit.b4     /* Receive CRC enable bit */
2449
#define     rshte_g1erc       g1erc_addr.bit.b5     /* Receive shift operation enable bit */
2450
#define     rbsf0_g1erc       g1erc_addr.bit.b6     /* Receive bit stuffing "1" delete select bit */
2451
#define     rbsf1_g1erc       g1erc_addr.bit.b7     /* Receive bit stuffing "0" delete select bit */
2452
2453
/*------------------------------------------------------
2454
    SI/O Special Communication Interrupt Detect Register 1
2455
------------------------------------------------------*/
2456
union byte_def g1irf_addr;
2457
#define     g1irf       g1irf_addr.byte
2458
                                                    /* (b1-b0) Reserved bit (Set to 0) */
2459
#define     bserr_g1irf       g1irf_addr.bit.b2     /* Bit stuffing error detect flag */
2460
#define     abt_g1irf         g1irf_addr.bit.b3     /* Arbitration lost detect flag */
2461
#define     irf0_g1irf        g1irf_addr.bit.b4     /* Interrupt cause determination flag 0 */
2462
#define     irf1_g1irf        g1irf_addr.bit.b5     /* Interrupt cause determination flag 1 */
2463
#define     irf2_g1irf        g1irf_addr.bit.b6     /* Interrupt cause determination flag 2 */
2464
#define     irf3_g1irf        g1irf_addr.bit.b7     /* Interrupt cause determination flag 3 */
2465
2466
/*------------------------------------------------------
2467
     Receive Data Register 1
2468
------------------------------------------------------*/
2469
union byte_def g1dr_addr;
2470
#define     g1dr       g1dr_addr.byte
2471
2472
2473
/*------------------------------------------------------
2474
    Transmit Buffer Register 1
2475
------------------------------------------------------*/
2476
union byte_def g1tb_addr;
2477
#define     g1tb       g1tb_addr.byte
2478
2479
/*------------------------------------------------------
2480
    Data Compare Register 10
2481
------------------------------------------------------*/
2482
union byte_def g1cmp0_addr;
2483
#define     g1cmp0       g1cmp0_addr.byte
2484
2485
/*------------------------------------------------------
2486
    Data Compare Register 11
2487
------------------------------------------------------*/
2488
union byte_def g1cmp1_addr;
2489
#define     g1cmp1       g1cmp1_addr.byte
2490
2491
/*------------------------------------------------------
2492
    Data Compare Register 12
2493
------------------------------------------------------*/
2494
union byte_def g1cmp2_addr;
2495
#define     g1cmp2       g1cmp2_addr.byte
2496
2497
/*------------------------------------------------------
2498
    Data Compare Register 13
2499
------------------------------------------------------*/
2500
union byte_def g1cmp3_addr;
2501
#define     g1cmp3       g1cmp3_addr.byte
2502
2503
/*------------------------------------------------------
2504
    Data Mask Register 10
2505
------------------------------------------------------*/
2506
union byte_def g1msk0_addr;
2507
#define     g1msk0       g1msk0_addr.byte
2508
2509
/*------------------------------------------------------
2510
    Data Mask Register 11
2511
------------------------------------------------------*/
2512
union byte_def g1msk1_addr;
2513
#define     g1msk1       g1msk1_addr.byte
2514
2515
/*------------------------------------------------------
2516
    Transmit Output Register 1
2517
------------------------------------------------------*/
2518
union byte_def g1to_addr;
2519
#define     g1to       g1to_addr.byte
2520
2521
/*------------------------------------------------------
2522
    Receive Input Register 0
2523
------------------------------------------------------*/
2524
union byte_def g1ri_addr;
2525
#define     g1ri       g1ri_addr.byte
2526
2527
2528
/*------------------------------------------------------
2529
    Input Function Select Register
2530
------------------------------------------------------*/
2531
union byte_def ips_addr;
2532
#define     ips      ips_addr.byte
2533
#define     ips0     ips_addr.bit.b0    /* Communication unit 0 input pin select bit 0 */
2534
#define     ips1     ips_addr.bit.b1    /* Communication unit 1 input pin select bit 1 */
2535
#define     ips2     ips_addr.bit.b2    /* Port P15 input peripheral function select bit */
2536
#define     ips3     ips_addr.bit.b3    /* CAN0in function pin select bit */
2537
#define     ips4     ips_addr.bit.b4
2538
#define     ips5     ips_addr.bit.b5
2539
#define     ips6     ips_addr.bit.b6
2540
                                        /* (b7) Reserved bit (Set to 0) */
2541
2542
/*------------------------------------------------------
2543
    Input Function Select Register A
2544
------------------------------------------------------*/
2545
union byte_def ipsa_addr;
2546
#define     ipsa     ipsa_addr.byte
2547
#define     ipsa_0   ipsa_addr.bit.b0   /* II/O 2-phase pulse input pin select bit */
2548
                                        /* (b2-b1) Reserved bit (Set to 0) */
2549
#define     ipsa_3   ipsa_addr.bit.b3   /* CAN1in function pin select bit */
2550
                                        /* (b7-b4) Reserved bit (Set to 0) */
2551
2552
/*------------------------------------------------------
2553
    Input Function Select Register A
2554
------------------------------------------------------*/
2555
union byte_def ipsb_addr;
2556
#define     ipsb     ipsb_addr.byte
2557
#define     ipsb_0   ipsb_addr.bit.b0   /* Port P15 input peripheral function select bit */
2558
#define     ipsb_1   ipsb_addr.bit.b1   /* Port P15 input peripheral function select bit */
2559
#define     ipsb_2   ipsb_addr.bit.b2   /* Port P15 input peripheral function select bit */
2560
#define     ipsb_3   ipsb_addr.bit.b3   /* Port P15 input peripheral function select bit */
2561
#define     ipsb_4   ipsb_addr.bit.b4   /* Port P15 input peripheral function select bit */
2562
#define     ipsb_5   ipsb_addr.bit.b5   /* Port P15 input peripheral function select bit */
2563
#define     ipsb_6   ipsb_addr.bit.b6   /* Port P15 input peripheral function select bit */
2564
#define     ipsb_7   ipsb_addr.bit.b7   /* Port P15 input peripheral function select bit */
2565
2566
2567
2568
/*------------------------------------------------------
2569
    PLL Control Register
2570
------------------------------------------------------*/
2571
#define     plc         plc_addr.word
2572
2573
union byte_def plc0_addr;
2574
#define     plc0    plc0_addr.byte
2575
2576
#define     plc00   plc0_addr.bit.b0    /* (b2-b0) Programmable counter select bit */
2577
#define     plc01   plc0_addr.bit.b1
2578
#define     plc02   plc0_addr.bit.b2
2579
                                        /* (b3) Reserved bit (Set to 0) */
2580
                                        /* (b4) Reserved bit (Set to 1) */
2581
                                        /* (b5) Reserved bit (Set to 0) */
2582
                                        /* (b6) Reserved bit (Set to 1) */
2583
#define     plc07   plc0_addr.bit.b7    /* Operation enable bit */
2584
2585
/*------------------------------------------------------
2586
    PLL Control Register 1
2587
------------------------------------------------------*/
2588
union byte_def plc1_addr;
2589
#define     plc1    plc1_addr.byte
2590
                                        /* (b0) Reserved bit (Set to 0) */
2591
                                        /* (b1) Reserved bit (Set to 1) */
2592
#define     plc12   plc1_addr.bit.b2    /* PLL clock division switch bit */
2593
                                        /* (b3) Reserved bit (Set to 0) */
2594
                                        /* (b4) Reserved bit (Set to 0) */
2595
                                        /* (b7-b5) Reserved bit (Set to 0) */
2596
2597
/*------------------------------------------------------
2598
    Voltage Down Detection Interrupt Register
2599
------------------------------------------------------*/
2600
union byte_def d4int_addr;
2601
#define     d4int   d4int_addr.byte
2602
2603
#define     d40     d4int_addr.bit.b0   /* Voltage down detection interrupt enable bit */
2604
#define     d41     d4int_addr.bit.b1   /* STOP-WAIT mode deactivation control bit */
2605
#define     d42     d4int_addr.bit.b2   /* Voltage change detection flag */
2606
#define     d43     d4int_addr.bit.b3   /* WDT overflow detect flag */
2607
#define     df0     d4int_addr.bit.b4   /* (b5-b4) Sampling clock select bit */
2608
#define     df1     d4int_addr.bit.b5
2609
                                        /* (b7-b6) Reserved bit (Set to 0) */
2610
2611
2612
/*------------------------------------------------------
2613
    Port P0
2614
------------------------------------------------------*/
2615
union byte_def p0_addr;
2616
#define     p0      p0_addr.byte
2617
2618
#define     p0_0        p0_addr.bit.b0      /* Port P0  bit0 */
2619
#define     p0_1        p0_addr.bit.b1      /* Port P0  bit1 */
2620
#define     p0_2        p0_addr.bit.b2      /* Port P0  bit2 */
2621
#define     p0_3        p0_addr.bit.b3      /* Port P0  bit3 */
2622
#define     p0_4        p0_addr.bit.b4      /* Port P0  bit4 */
2623
#define     p0_5        p0_addr.bit.b5      /* Port P0  bit5 */
2624
#define     p0_6        p0_addr.bit.b6      /* Port P0  bit6 */
2625
#define     p0_7        p0_addr.bit.b7      /* Port P0  bit7 */
2626
2627
/*------------------------------------------------------
2628
    Port P0 direction register
2629
------------------------------------------------------*/
2630
union byte_def pd0_addr;
2631
#define     pd0     pd0_addr.byte
2632
2633
#define     pd0_0       pd0_addr.bit.b0     /* P0 direction register  bit0 */
2634
#define     pd0_1       pd0_addr.bit.b1     /* P0 direction register  bit1 */
2635
#define     pd0_2       pd0_addr.bit.b2     /* P0 direction register  bit2 */
2636
#define     pd0_3       pd0_addr.bit.b3     /* P0 direction register  bit3 */
2637
#define     pd0_4       pd0_addr.bit.b4     /* P0 direction register  bit4 */
2638
#define     pd0_5       pd0_addr.bit.b5     /* P0 direction register  bit5 */
2639
#define     pd0_6       pd0_addr.bit.b6     /* P0 direction register  bit6 */
2640
#define     pd0_7       pd0_addr.bit.b7     /* P0 direction register  bit7 */
2641
2642
/*------------------------------------------------------
2643
    Port P1
2644
------------------------------------------------------*/
2645
union byte_def p1_addr;
2646
#define     p1      p1_addr.byte
2647
2648
#define     p1_0        p1_addr.bit.b0      /* Port P1  bit0 */
2649
#define     p1_1        p1_addr.bit.b1      /* Port P1  bit1 */
2650
#define     p1_2        p1_addr.bit.b2      /* Port P1  bit2 */
2651
#define     p1_3        p1_addr.bit.b3      /* Port P1  bit3 */
2652
#define     p1_4        p1_addr.bit.b4      /* Port P1  bit4 */
2653
#define     p1_5        p1_addr.bit.b5      /* Port P1  bit5 */
2654
#define     p1_6        p1_addr.bit.b6      /* Port P1  bit6 */
2655
#define     p1_7        p1_addr.bit.b7      /* Port P1  bit7 */
2656
2657
/*------------------------------------------------------
2658
    Port P1 direction register
2659
------------------------------------------------------*/
2660
union byte_def pd1_addr;
2661
#define     pd1     pd1_addr.byte
2662
2663
#define     pd1_0       pd1_addr.bit.b0     /* P1 direction register  bit0 */
2664
#define     pd1_1       pd1_addr.bit.b1     /* P1 direction register  bit1 */
2665
#define     pd1_2       pd1_addr.bit.b2     /* P1 direction register  bit2 */
2666
#define     pd1_3       pd1_addr.bit.b3     /* P1 direction register  bit3 */
2667
#define     pd1_4       pd1_addr.bit.b4     /* P1 direction register  bit4 */
2668
#define     pd1_5       pd1_addr.bit.b5     /* P1 direction register  bit5 */
2669
#define     pd1_6       pd1_addr.bit.b6     /* P1 direction register  bit6 */
2670
#define     pd1_7       pd1_addr.bit.b7     /* P1 direction register  bit7 */
2671
2672
/*------------------------------------------------------
2673
    Port P2
2674
------------------------------------------------------*/
2675
union byte_def p2_addr;
2676
#define     p2      p2_addr.byte
2677
2678
#define     p2_0        p2_addr.bit.b0      /* Port P2  bit0 */
2679
#define     p2_1        p2_addr.bit.b1      /* Port P2  bit1 */
2680
#define     p2_2        p2_addr.bit.b2      /* Port P2  bit2 */
2681
#define     p2_3        p2_addr.bit.b3      /* Port P2  bit3 */
2682
#define     p2_4        p2_addr.bit.b4      /* Port P2  bit4 */
2683
#define     p2_5        p2_addr.bit.b5      /* Port P2  bit5 */
2684
#define     p2_6        p2_addr.bit.b6      /* Port P2  bit6 */
2685
#define     p2_7        p2_addr.bit.b7      /* Port P2  bit7 */
2686
2687
/*------------------------------------------------------
2688
    Port P2 direction register
2689
------------------------------------------------------*/
2690
union byte_def pd2_addr;
2691
#define     pd2     pd2_addr.byte
2692
2693
#define     pd2_0       pd2_addr.bit.b0     /* P2 direction register  bit0 */
2694
#define     pd2_1       pd2_addr.bit.b1     /* P2 direction register  bit1 */
2695
#define     pd2_2       pd2_addr.bit.b2     /* P2 direction register  bit2 */
2696
#define     pd2_3       pd2_addr.bit.b3     /* P2 direction register  bit3 */
2697
#define     pd2_4       pd2_addr.bit.b4     /* P2 direction register  bit4 */
2698
#define     pd2_5       pd2_addr.bit.b5     /* P2 direction register  bit5 */
2699
#define     pd2_6       pd2_addr.bit.b6     /* P2 direction register  bit6 */
2700
#define     pd2_7       pd2_addr.bit.b7     /* P2 direction register  bit7 */
2701
2702
/*------------------------------------------------------
2703
    Port P3
2704
------------------------------------------------------*/
2705
union byte_def p3_addr;
2706
#define     p3      p3_addr.byte
2707
2708
#define     p3_0        p3_addr.bit.b0      /* Port P3  bit0 */
2709
#define     p3_1        p3_addr.bit.b1      /* Port P3  bit1 */
2710
#define     p3_2        p3_addr.bit.b2      /* Port P3  bit2 */
2711
#define     p3_3        p3_addr.bit.b3      /* Port P3  bit3 */
2712
#define     p3_4        p3_addr.bit.b4      /* Port P3  bit4 */
2713
#define     p3_5        p3_addr.bit.b5      /* Port P3  bit5 */
2714
#define     p3_6        p3_addr.bit.b6      /* Port P3  bit6 */
2715
#define     p3_7        p3_addr.bit.b7      /* Port P3  bit7 */
2716
2717
/*------------------------------------------------------
2718
    Port P3 direction register
2719
------------------------------------------------------*/
2720
union byte_def pd3_addr;
2721
#define     pd3     pd3_addr.byte
2722
2723
#define     pd3_0       pd3_addr.bit.b0     /* P3 direction register  bit0 */
2724
#define     pd3_1       pd3_addr.bit.b1     /* P3 direction register  bit1 */
2725
#define     pd3_2       pd3_addr.bit.b2     /* P3 direction register  bit2 */
2726
#define     pd3_3       pd3_addr.bit.b3     /* P3 direction register  bit3 */
2727
#define     pd3_4       pd3_addr.bit.b4     /* P3 direction register  bit4 */
2728
#define     pd3_5       pd3_addr.bit.b5     /* P3 direction register  bit5 */
2729
#define     pd3_6       pd3_addr.bit.b6     /* P3 direction register  bit6 */
2730
#define     pd3_7       pd3_addr.bit.b7     /* P3 direction register  bit7 */
2731
2732
/*------------------------------------------------------
2733
    Port P4
2734
------------------------------------------------------*/
2735
union byte_def p4_addr;
2736
#define     p4      p4_addr.byte
2737
2738
#define     p4_0        p4_addr.bit.b0      /* Port P4  bit0 */
2739
#define     p4_1        p4_addr.bit.b1      /* Port P4  bit1 */
2740
#define     p4_2        p4_addr.bit.b2      /* Port P4  bit2 */
2741
#define     p4_3        p4_addr.bit.b3      /* Port P4  bit3 */
2742
#define     p4_4        p4_addr.bit.b4      /* Port P4  bit4 */
2743
#define     p4_5        p4_addr.bit.b5      /* Port P4  bit5 */
2744
#define     p4_6        p4_addr.bit.b6      /* Port P4  bit6 */
2745
#define     p4_7        p4_addr.bit.b7      /* Port P4  bit7 */
2746
2747
/*------------------------------------------------------
2748
    Port P4 direction register
2749
------------------------------------------------------*/
2750
union byte_def pd4_addr;
2751
#define     pd4     pd4_addr.byte
2752
2753
#define     pd4_0       pd4_addr.bit.b0     /* P4 direction register  bit0 */
2754
#define     pd4_1       pd4_addr.bit.b1     /* P4 direction register  bit1 */
2755
#define     pd4_2       pd4_addr.bit.b2     /* P4 direction register  bit2 */
2756
#define     pd4_3       pd4_addr.bit.b3     /* P4 direction register  bit3 */
2757
#define     pd4_4       pd4_addr.bit.b4     /* P4 direction register  bit4 */
2758
#define     pd4_5       pd4_addr.bit.b5     /* P4 direction register  bit5 */
2759
#define     pd4_6       pd4_addr.bit.b6     /* P4 direction register  bit6 */
2760
#define     pd4_7       pd4_addr.bit.b7     /* P4 direction register  bit7 */
2761
2762
/*------------------------------------------------------
2763
    Port P5
2764
------------------------------------------------------*/
2765
union byte_def p5_addr;
2766
#define     p5      p5_addr.byte
2767
2768
#define     p5_0        p5_addr.bit.b0      /* Port P5  bit0 */
2769
#define     p5_1        p5_addr.bit.b1      /* Port P5  bit1 */
2770
#define     p5_2        p5_addr.bit.b2      /* Port P5  bit2 */
2771
#define     p5_3        p5_addr.bit.b3      /* Port P5  bit3 */
2772
#define     p5_4        p5_addr.bit.b4      /* Port P5  bit4 */
2773
#define     p5_5        p5_addr.bit.b5      /* Port P5  bit5 */
2774
#define     p5_6        p5_addr.bit.b6      /* Port P5  bit6 */
2775
#define     p5_7        p5_addr.bit.b7      /* Port P5  bit7 */
2776
2777
/*------------------------------------------------------
2778
    Port P5 direction register
2779
------------------------------------------------------*/
2780
union byte_def pd5_addr;
2781
#define     pd5     pd5_addr.byte
2782
2783
#define     pd5_0       pd5_addr.bit.b0     /* P5 direction register  bit0 */
2784
#define     pd5_1       pd5_addr.bit.b1     /* P5 direction register  bit1 */
2785
#define     pd5_2       pd5_addr.bit.b2     /* P5 direction register  bit2 */
2786
#define     pd5_3       pd5_addr.bit.b3     /* P5 direction register  bit3 */
2787
#define     pd5_4       pd5_addr.bit.b4     /* P5 direction register  bit4 */
2788
#define     pd5_5       pd5_addr.bit.b5     /* P5 direction register  bit5 */
2789
#define     pd5_6       pd5_addr.bit.b6     /* P5 direction register  bit6 */
2790
#define     pd5_7       pd5_addr.bit.b7     /* P5 direction register  bit7 */
2791
2792
/*------------------------------------------------------
2793
    Port P6
2794
------------------------------------------------------*/
2795
union byte_def p6_addr;
2796
#define     p6      p6_addr.byte
2797
2798
#define     p6_0        p6_addr.bit.b0      /* Port P6  bit0 */
2799
#define     p6_1        p6_addr.bit.b1      /* Port P6  bit1 */
2800
#define     p6_2        p6_addr.bit.b2      /* Port P6  bit2 */
2801
#define     p6_3        p6_addr.bit.b3      /* Port P6  bit3 */
2802
#define     p6_4        p6_addr.bit.b4      /* Port P6  bit4 */
2803
#define     p6_5        p6_addr.bit.b5      /* Port P6  bit5 */
2804
#define     p6_6        p6_addr.bit.b6      /* Port P6  bit6 */
2805
#define     p6_7        p6_addr.bit.b7      /* Port P6  bit7 */
2806
2807
/*------------------------------------------------------
2808
    Port P6 direction register
2809
------------------------------------------------------*/
2810
union byte_def pd6_addr;
2811
#define     pd6     pd6_addr.byte
2812
2813
#define     pd6_0       pd6_addr.bit.b0     /* P6 direction register  bit0 */
2814
#define     pd6_1       pd6_addr.bit.b1     /* P6 direction register  bit1 */
2815
#define     pd6_2       pd6_addr.bit.b2     /* P6 direction register  bit2 */
2816
#define     pd6_3       pd6_addr.bit.b3     /* P6 direction register  bit3 */
2817
#define     pd6_4       pd6_addr.bit.b4     /* P6 direction register  bit4 */
2818
#define     pd6_5       pd6_addr.bit.b5     /* P6 direction register  bit5 */
2819
#define     pd6_6       pd6_addr.bit.b6     /* P6 direction register  bit6 */
2820
#define     pd6_7       pd6_addr.bit.b7     /* P6 direction register  bit7 */
2821
2822
/*------------------------------------------------------
2823
    Port P7
2824
------------------------------------------------------*/
2825
union byte_def p7_addr;
2826
#define     p7      p7_addr.byte
2827
2828
#define     p7_0        p7_addr.bit.b0      /* Port P7  bit0 */
2829
#define     p7_1        p7_addr.bit.b1      /* Port P7  bit1 */
2830
#define     p7_2        p7_addr.bit.b2      /* Port P7  bit2 */
2831
#define     p7_3        p7_addr.bit.b3      /* Port P7  bit3 */
2832
#define     p7_4        p7_addr.bit.b4      /* Port P7  bit4 */
2833
#define     p7_5        p7_addr.bit.b5      /* Port P7  bit5 */
2834
#define     p7_6        p7_addr.bit.b6      /* Port P7  bit6 */
2835
#define     p7_7        p7_addr.bit.b7      /* Port P7  bit7 */
2836
2837
/*------------------------------------------------------
2838
    Port P7 direction register
2839
------------------------------------------------------*/
2840
union byte_def pd7_addr;
2841
#define     pd7     pd7_addr.byte
2842
2843
#define     pd7_0       pd7_addr.bit.b0     /* P7 direction register  bit0 */
2844
#define     pd7_1       pd7_addr.bit.b1     /* P7 direction register  bit1 */
2845
#define     pd7_2       pd7_addr.bit.b2     /* P7 direction register  bit2 */
2846
#define     pd7_3       pd7_addr.bit.b3     /* P7 direction register  bit3 */
2847
#define     pd7_4       pd7_addr.bit.b4     /* P7 direction register  bit4 */
2848
#define     pd7_5       pd7_addr.bit.b5     /* P7 direction register  bit5 */
2849
#define     pd7_6       pd7_addr.bit.b6     /* P7 direction register  bit6 */
2850
#define     pd7_7       pd7_addr.bit.b7     /* P7 direction register  bit7 */
2851
2852
/*------------------------------------------------------
2853
    Port P8
2854
------------------------------------------------------*/
2855
union byte_def p8_addr;
2856
#define     p8      p8_addr.byte
2857
2858
#define     p8_0        p8_addr.bit.b0      /* Port P8  bit0 */
2859
#define     p8_1        p8_addr.bit.b1      /* Port P8  bit1 */
2860
#define     p8_2        p8_addr.bit.b2      /* Port P8  bit2 */
2861
#define     p8_3        p8_addr.bit.b3      /* Port P8  bit3 */
2862
#define     p8_4        p8_addr.bit.b4      /* Port P8  bit4 */
2863
#define     p8_5        p8_addr.bit.b5      /* Port P8  bit5 */
2864
#define     p8_6        p8_addr.bit.b6      /* Port P8  bit6 */
2865
#define     p8_7        p8_addr.bit.b7      /* Port P8  bit7 */
2866
2867
/*------------------------------------------------------
2868
    Port P8 direction register
2869
------------------------------------------------------*/
2870
union byte_def pd8_addr;
2871
#define     pd8     pd8_addr.byte
2872
2873
#define     pd8_0       pd8_addr.bit.b0     /* P8 direction register  bit0 */
2874
#define     pd8_1       pd8_addr.bit.b1     /* P8 direction register  bit1 */
2875
#define     pd8_2       pd8_addr.bit.b2     /* P8 direction register  bit2 */
2876
#define     pd8_3       pd8_addr.bit.b3     /* P8 direction register  bit3 */
2877
#define     pd8_4       pd8_addr.bit.b4     /* P8 direction register  bit4 */
2878
                                            /* (b5) Nothing is assigned */
2879
#define     pd8_6       pd8_addr.bit.b6     /* P8 direction register  bit6 */
2880
#define     pd8_7       pd8_addr.bit.b7     /* P8 direction register  bit7 */
2881
2882
/*------------------------------------------------------
2883
    Port P9
2884
------------------------------------------------------*/
2885
union byte_def p9_addr;
2886
#define     p9      p9_addr.byte
2887
2888
#define     p9_0        p9_addr.bit.b0      /* Port P9  bit0 */
2889
#define     p9_1        p9_addr.bit.b1      /* Port P9  bit1 */
2890
#define     p9_2        p9_addr.bit.b2      /* Port P9  bit2 */
2891
#define     p9_3        p9_addr.bit.b3      /* Port P9  bit3 */
2892
#define     p9_4        p9_addr.bit.b4      /* Port P9  bit4 */
2893
#define     p9_5        p9_addr.bit.b5      /* Port P9  bit5 */
2894
#define     p9_6        p9_addr.bit.b6      /* Port P9  bit6 */
2895
#define     p9_7        p9_addr.bit.b7      /* Port P9  bit7 */
2896
2897
/*------------------------------------------------------
2898
    Port P9 direction register
2899
------------------------------------------------------*/
2900
union byte_def pd9_addr;
2901
#define     pd9     pd9_addr.byte
2902
2903
#define     pd9_0       pd9_addr.bit.b0     /* P9 direction register  bit0 */
2904
#define     pd9_1       pd9_addr.bit.b1     /* P9 direction register  bit1 */
2905
#define     pd9_2       pd9_addr.bit.b2     /* P9 direction register  bit2 */
2906
#define     pd9_3       pd9_addr.bit.b3     /* P9 direction register  bit3 */
2907
#define     pd9_4       pd9_addr.bit.b4     /* P9 direction register  bit4 */
2908
#define     pd9_5       pd9_addr.bit.b5     /* P9 direction register  bit5 */
2909
#define     pd9_6       pd9_addr.bit.b6     /* P9 direction register  bit6 */
2910
#define     pd9_7       pd9_addr.bit.b7     /* P9 direction register  bit7 */
2911
2912
/*------------------------------------------------------
2913
    Port P10
2914
------------------------------------------------------*/
2915
union byte_def p10_addr;
2916
#define     p10     p10_addr.byte
2917
2918
#define     p10_0       p10_addr.bit.b0     /* Port P10  bit0 */
2919
#define     p10_1       p10_addr.bit.b1     /* Port P10  bit1 */
2920
#define     p10_2       p10_addr.bit.b2     /* Port P10  bit2 */
2921
#define     p10_3       p10_addr.bit.b3     /* Port P10  bit3 */
2922
#define     p10_4       p10_addr.bit.b4     /* Port P10  bit4 */
2923
#define     p10_5       p10_addr.bit.b5     /* Port P10  bit5 */
2924
#define     p10_6       p10_addr.bit.b6     /* Port P10  bit6 */
2925
#define     p10_7       p10_addr.bit.b7     /* Port P10  bit7 */
2926
2927
/*------------------------------------------------------
2928
    Port P10 direction register
2929
------------------------------------------------------*/
2930
union byte_def pd10_addr;
2931
#define     pd10        pd10_addr.byte
2932
2933
#define     pd10_0      pd10_addr.bit.b0    /* P10 direction register  bit0 */
2934
#define     pd10_1      pd10_addr.bit.b1    /* P10 direction register  bit1 */
2935
#define     pd10_2      pd10_addr.bit.b2    /* P10 direction register  bit2 */
2936
#define     pd10_3      pd10_addr.bit.b3    /* P10 direction register  bit3 */
2937
#define     pd10_4      pd10_addr.bit.b4    /* P10 direction register  bit4 */
2938
#define     pd10_5      pd10_addr.bit.b5    /* P10 direction register  bit5 */
2939
#define     pd10_6      pd10_addr.bit.b6    /* P10 direction register  bit6 */
2940
#define     pd10_7      pd10_addr.bit.b7    /* P10 direction register  bit7 */
2941
2942
/*------------------------------------------------------
2943
    Port P11
2944
------------------------------------------------------*/
2945
union byte_def p11_addr;
2946
#define     p11     p11_addr.byte
2947
2948
#define     p11_0       p11_addr.bit.b0     /* Port P11  bit0 */
2949
#define     p11_1       p11_addr.bit.b1     /* Port P11  bit1 */
2950
#define     p11_2       p11_addr.bit.b2     /* Port P11  bit2 */
2951
#define     p11_3       p11_addr.bit.b3     /* Port P11  bit3 */
2952
#define     p11_4       p11_addr.bit.b4     /* Port P11  bit4 */
2953
                                            /* (b7-b5) Nothing is assigned */
2954
2955
/*------------------------------------------------------
2956
    Port P11 direction register
2957
------------------------------------------------------*/
2958
union byte_def pd11_addr;
2959
#define     pd11        pd11_addr.byte
2960
2961
#define     pd11_0      pd11_addr.bit.b0    /* P11 direction register  bit0 */
2962
#define     pd11_1      pd11_addr.bit.b1    /* P11 direction register  bit1 */
2963
#define     pd11_2      pd11_addr.bit.b2    /* P11 direction register  bit2 */
2964
#define     pd11_3      pd11_addr.bit.b3    /* P11 direction register  bit3 */
2965
#define     pd11_4      pd11_addr.bit.b4    /* P11 direction register  bit4 */
2966
                                            /* (b7-b5) Nothing is assigned */
2967
2968
/*------------------------------------------------------
2969
    Port P12
2970
------------------------------------------------------*/
2971
union byte_def p12_addr;
2972
#define     p12     p12_addr.byte
2973
2974
#define     p12_0       p12_addr.bit.b0     /* Port P12  bit0 */
2975
#define     p12_1       p12_addr.bit.b1     /* Port P12  bit1 */
2976
#define     p12_2       p12_addr.bit.b2     /* Port P12  bit2 */
2977
#define     p12_3       p12_addr.bit.b3     /* Port P12  bit3 */
2978
#define     p12_4       p12_addr.bit.b4     /* Port P12  bit4 */
2979
#define     p12_5       p12_addr.bit.b5     /* Port P12  bit5 */
2980
#define     p12_6       p12_addr.bit.b6     /* Port P12  bit6 */
2981
#define     p12_7       p12_addr.bit.b7     /* Port P12  bit7 */
2982
2983
/*------------------------------------------------------
2984
    Port P12 direction register
2985
------------------------------------------------------*/
2986
union byte_def pd12_addr;
2987
#define     pd12        pd12_addr.byte
2988
2989
#define     pd12_0      pd12_addr.bit.b0    /* P12 direction register  bit0 */
2990
#define     pd12_1      pd12_addr.bit.b1    /* P12 direction register  bit1 */
2991
#define     pd12_2      pd12_addr.bit.b2    /* P12 direction register  bit2 */
2992
#define     pd12_3      pd12_addr.bit.b3    /* P12 direction register  bit3 */
2993
#define     pd12_4      pd12_addr.bit.b4    /* P12 direction register  bit4 */
2994
#define     pd12_5      pd12_addr.bit.b5    /* P12 direction register  bit5 */
2995
#define     pd12_6      pd12_addr.bit.b6    /* P12 direction register  bit6 */
2996
#define     pd12_7      pd12_addr.bit.b7    /* P12 direction register  bit7 */
2997
2998
/*------------------------------------------------------
2999
    Port P13
3000
------------------------------------------------------*/
3001
union byte_def p13_addr;
3002
#define     p13     p13_addr.byte
3003
3004
#define     p13_0       p13_addr.bit.b0     /* Port P13  bit0 */
3005
#define     p13_1       p13_addr.bit.b1     /* Port P13  bit1 */
3006
#define     p13_2       p13_addr.bit.b2     /* Port P13  bit2 */
3007
#define     p13_3       p13_addr.bit.b3     /* Port P13  bit3 */
3008
#define     p13_4       p13_addr.bit.b4     /* Port P13  bit4 */
3009
#define     p13_5       p13_addr.bit.b5     /* Port P13  bit5 */
3010
#define     p13_6       p13_addr.bit.b6     /* Port P13  bit6 */
3011
#define     p13_7       p13_addr.bit.b7     /* Port P13  bit7 */
3012
3013
/*------------------------------------------------------
3014
    Port P13 direction register
3015
------------------------------------------------------*/
3016
union byte_def pd13_addr;
3017
#define     pd13        pd13_addr.byte
3018
3019
#define     pd13_0      pd13_addr.bit.b0    /* P13 direction register  bit0 */
3020
#define     pd13_1      pd13_addr.bit.b1    /* P13 direction register  bit1 */
3021
#define     pd13_2      pd13_addr.bit.b2    /* P13 direction register  bit2 */
3022
#define     pd13_3      pd13_addr.bit.b3    /* P13 direction register  bit3 */
3023
#define     pd13_4      pd13_addr.bit.b4    /* P13 direction register  bit4 */
3024
#define     pd13_5      pd13_addr.bit.b5    /* P13 direction register  bit5 */
3025
#define     pd13_6      pd13_addr.bit.b6    /* P13 direction register  bit6 */
3026
#define     pd13_7      pd13_addr.bit.b7    /* P13 direction register  bit7 */
3027
3028
/*------------------------------------------------------
3029
    Port P14
3030
------------------------------------------------------*/
3031
union byte_def p14_addr;
3032
#define     p14     p14_addr.byte
3033
3034
#define     p14_0       p14_addr.bit.b0     /* Port P14  bit0 */
3035
#define     p14_1       p14_addr.bit.b1     /* Port P14  bit1 */
3036
#define     p14_2       p14_addr.bit.b2     /* Port P14  bit2 */
3037
#define     p14_3       p14_addr.bit.b3     /* Port P14  bit3 */
3038
#define     p14_4       p14_addr.bit.b4     /* Port P14  bit4 */
3039
#define     p14_5       p14_addr.bit.b5     /* Port P14  bit5 */
3040
#define     p14_6       p14_addr.bit.b6     /* Port P14  bit6 */
3041
                                            /* (b7) Nothing is assigned */
3042
3043
/*------------------------------------------------------
3044
    Port P14 direction register
3045
------------------------------------------------------*/
3046
union byte_def pd14_addr;
3047
#define     pd14        pd14_addr.byte
3048
3049
#define     pd14_0      pd14_addr.bit.b0    /* P14 direction register  bit0 */
3050
#define     pd14_1      pd14_addr.bit.b1    /* P14 direction register  bit1 */
3051
#define     pd14_2      pd14_addr.bit.b2    /* P14 direction register  bit2 */
3052
#define     pd14_3      pd14_addr.bit.b3    /* P14 direction register  bit3 */
3053
#define     pd14_4      pd14_addr.bit.b4    /* P14 direction register  bit4 */
3054
#define     pd14_5      pd14_addr.bit.b5    /* P14 direction register  bit5 */
3055
#define     pd14_6      pd14_addr.bit.b6    /* P14 direction register  bit6 */
3056
                                            /* (b7) Nothing is assigned */
3057
3058
/*------------------------------------------------------
3059
    Port P15
3060
------------------------------------------------------*/
3061
union byte_d