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1 2 jalaffon
/************************************************************************
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*                                                                       *
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*   file name   : definition of M32C/80's SFR                           *
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*                                                                       *
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*   Copyright, 2003 RENESAS TECHNOLOGY CORPORATION                      *
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*                   AND RENESAS SOLUTIONS CORPORATION                   *
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*                                                                       *
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*   Version     : 1.01  ( 2002-06-28)                                   *
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*                 1.02  ( 2002-07-09)                                   *
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*                 1.03  ( 2002-09-19)                                   *
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*                   change:                                             *
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*                       delete same symbol name                         *
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*                 1.04  ( 2003-10-15)                                   *
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*                   change:                                             *
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*                           pu32        pur3_addr.bit.b1                *
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*                            -> pu32        pur3_addr.bit.b2            *
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*                           pu33        pur3_addr.bit.b1                *
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*                            -> pu33        pur3_addr.bit.b3            *
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*                           pu34        pur3_addr.bit.b1                *
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*                            -> pu34        pur3_addr.bit.b4            *
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*                           pu35        pur3_addr.bit.b1                *
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*                            -> pu35        pur3_addr.bit.b5            *
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*                           pu36        pur3_addr.bit.b1                *
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*                            -> pu36        pur3_addr.bit.b6            *
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*                           pu37        pur3_addr.bit.b1                *
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*                            -> pu37        pur3_addr.bit.b7            *
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*                           pu42        pur4_addr.bit.b1                *
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*                            -> pu42        pur4_addr.bit.b2            *
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*                           pu43        pur4_addr.bit.b1                *
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*                            -> pu43        pur4_addr.bit.b3            *
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*                                                                       *
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*************************************************************************/
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/*
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  note:
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    This data is a freeware that SFR for M32C/80 groups is described.
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    Renesas Technology Corporation and Renesas Solutions Corporation
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    assumes no responsibility for any damage that occurred by this data.
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*/
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/************************************************************************
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*   declare SFR address                                                 *
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************************************************************************/
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#pragma ADDRESS     pm0_addr        0004H       /* Processor mode register 0 */
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#pragma ADDRESS     pm1_addr        0005H       /* Processor mode register 1 */
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#pragma ADDRESS     cm0_addr        0006H       /* System clock control register 0 */
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#pragma ADDRESS     cm1_addr        0007H       /* System clock control register 1 */
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#pragma ADDRESS     wcr_addr        0008H       /* Wait control register */
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#pragma ADDRESS     aier_addr        0009H       /* Address match interrupt enable register */
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#pragma ADDRESS     prcr_addr        000aH       /* Protect register */
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#pragma ADDRESS     ds_addr                000bH       /* External data bus width control register */
51
#pragma ADDRESS     mcd_addr        000cH       /* Main clock division register */
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#pragma ADDRESS     cm2_addr        000dH       /* Oscillation stop detect register */
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#pragma ADDRESS     wdts_addr        000eH       /* Watchdog timer start register */
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#pragma ADDRESS     wdc_addr        000fH       /* Watchdog timer control register */
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#pragma ADDRESS     rmad0_addr        0010H       /* Address match interrupt register 0 */
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#pragma ADDRESS     rmad1_addr        0014H       /* Address match interrupt register 1 */
57
#pragma ADDRESS     plv_addr        0017H       /* PLL VDC control register */
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#pragma ADDRESS     rmad2_addr        0018H       /* Address match interrupt register 2 */
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#pragma ADDRESS     vdc0_addr        001bH       /* VDC control register 0 */
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#pragma ADDRESS     rmad3_addr        001cH       /* Address match interrupt register 3 */
61
#pragma ADDRESS                vdc1_addr        001fH                /* VDC control register 1 */
62
#pragma ADDRESS                eiad_addr        0020H                /* Emulator Exclusive Use Interrupt Register */
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#pragma ADDRESS                eitd_addr        0023H                /* Emulator Exclusive Use Interrupt Distinction Register*/
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#pragma ADDRESS                eprr_addr        0024H                /* Emulator Exclusive Use Protect Register*/
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#pragma ADDRESS                emu_addr        0025H                /* Emulator Setting Register*/
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#pragma ADDRESS                roa_addr        0030H                /* ROM Area Setting Register*/
67
#pragma ADDRESS                dba_addr        0031H                /* Debugging Monitor Setting Register*/
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#pragma ADDRESS                exa0_addr        0032H                /* Expansion Area Setting Register 0*/
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#pragma ADDRESS                exa1_addr        0033H                /* Expansion Area Setting Register 1*/
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#pragma ADDRESS                exa2_addr        0034H                /* Expansion Area Setting Register 2*/
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#pragma ADDRESS                exa3_addr        0035H                /* Expansion Area Setting Register 3*/
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#pragma ADDRESS     dramcont_addr    0040H  /* DRAM control register */
73
#pragma ADDRESS     refcnt_addr        0041H       /* DRAM refresh interval set register */
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#pragma ADDRESS                fmr2_addr        0055H                /* Flash Memory Control Register 2*/
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#pragma ADDRESS                fmr1_addr        0056H                /* Flash Memory Control Register 2*/
76
#pragma ADDRESS     fmr0_addr        0057H       /* Flash memory control register 0 */
77
#pragma ADDRESS     dm0ic_addr        0068H       /* DMA0 interrupt control register */
78
#pragma ADDRESS     tb5ic_addr  0069H       /* Timer B5 interrupt register */
79
#pragma ADDRESS     dm2ic_addr  006aH       /* DMA2 interrupt register */
80
#pragma ADDRESS     s2ric_addr  006bH       /* UART2 receive/ack interrupt control register */
81
#pragma ADDRESS     ta0ic_addr  006cH       /* Timer A0 interrupt control register */
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#pragma ADDRESS     s3ric_addr  006dH       /* UART3 receive/ack interrupt control register */
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#pragma ADDRESS     ta2ic_addr  006eH       /* Timer A2 interrupt control register */
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#pragma ADDRESS     s4ric_addr  006fH       /* UART4 receive/ack interrupt control register */
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#pragma ADDRESS     ta4ic_addr  0070H       /* Timer A4 interrupt control register */
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#pragma ADDRESS     bcn3ic_addr 0071H       /* Bus collision (UART3) interrupt control register */
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#pragma ADDRESS                bcn0ic_addr 0071H                /* Bus collision (UART0) interrupt control register */
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#pragma ADDRESS     s0ric_addr  0072H       /* UART0 receive interrupt control register */
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#pragma ADDRESS     ad0ic_addr  0073H       /* A/D0 conversion interrupt control register */
90
#pragma ADDRESS     s1ric_addr  0074H       /* UART1 receive interrupt control register */
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#pragma ADDRESS     iio0ic_addr 0075H       /* Intelligent I/O interrupt control register 0 */
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#pragma ADDRESS     tb1ic_addr  0076H       /* Timer B1 interrupt control register */
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#pragma ADDRESS     iio2ic_addr 0077H       /* Intelligent I/O interrupt control register 2 */
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#pragma ADDRESS     tb3ic_addr  0078H       /* Timer B3 interrupt control register */
95
#pragma ADDRESS     iio4ic_addr 0079H       /* Intelligent I/O interrupt control register 4 */
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#pragma ADDRESS     int5ic_addr 007aH       /* INT5~ interrupt control register */
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#pragma ADDRESS     iio6ic_addr 007bH       /* Intelligent I/O interrupt control register 6 */
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#pragma ADDRESS     int3ic_addr 007cH       /* INT3~ interrupt control register */
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#pragma ADDRESS     iio8ic_addr 007dH       /* Intelligent I/O interrupt control register 8 */
100
#pragma ADDRESS     int1ic_addr 007eH       /* INT1~ interrupt control register */
101
#pragma ADDRESS     iio10ic_addr 007fH      /* Intelligent I/O interrupt control register 10 */
102
#pragma ADDRESS                can1ic_addr 007fH                /* CAN1 Interrupt Control Register*/
103
#pragma ADDRESS     iio11ic_addr 0081H      /* Intelligent I/O interrupt control register 11 */
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#pragma ADDRESS                can2ic_addr 0081H                /* CAN2 Interrupt Control Register*/
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#pragma ADDRESS     ad1ic_addr  0086H       /* A/D1 conversion interrupt control register */
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#pragma ADDRESS     dm1ic_addr  0088H       /* DMA1 interrupt control register */
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#pragma ADDRESS     s2tic_addr  0089H       /* UART2 transmit/nack interrupt control register */
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#pragma ADDRESS     dm3ic_addr  008aH       /* DMA3 interrupt control register */
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#pragma ADDRESS     s3tic_addr  008bH       /* UART3 transmit/nack interrupt control register */
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#pragma ADDRESS     ta1ic_addr  008cH       /* Timer A1 interrupt control register */
111
#pragma ADDRESS     s4tic_addr  008dH       /* UART4 transmit/nack interrupt control register */
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#pragma ADDRESS     ta3ic_addr  008eH       /* Timer A3 interrupt control register */
113
#pragma ADDRESS     bcn2ic_addr 008fH       /* Bus collision (UART2) interrupt control register */
114
#pragma ADDRESS     s0tic_addr  0090H       /* UART0 transmit interrupt control register */
115
#pragma ADDRESS     bcn4ic_addr 0091H       /* Bus collision (UART4) interrupt control register */
116
#pragma ADDRESS                bcn1ic_addr 0091H                /* Bus collision (UART1) interrupt control register*/
117
#pragma ADDRESS     s1tic_addr  0092H       /* UART1 transmit interrupt control register */
118
#pragma ADDRESS     kupic_addr  0093H       /* Key input interrupt control register */
119
#pragma ADDRESS     tb0ic_addr  0094H       /* Timer B0 interrupt control register */
120
#pragma ADDRESS     iio1ic_addr 0095H       /* Intelligent I/O interrupt control register 1 */
121
#pragma ADDRESS     tb2ic_addr  0096H       /* Timer B2 interrupt control register */
122
#pragma ADDRESS     iio3ic_addr 0097H       /* Intelligent I/O interrupt control register 3 */
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#pragma ADDRESS     tb4ic_addr  0098H       /* Timer B4 interrupt control register */
124
#pragma ADDRESS     iio5ic_addr 0099H       /* Intelligent I/O interrupt control register 5 */
125
#pragma ADDRESS     int4ic_addr 009aH       /* INT4~ interrupt control register */
126
#pragma ADDRESS     iio7ic_addr 009bH       /* Intelligent I/O interrupt control register 7 */
127
#pragma ADDRESS     int2ic_addr 009cH       /* INT2~ interrupt control register */
128
#pragma ADDRESS     iio9ic_addr 009dH       /* Intelligent I/O interrupt control register 9 */
129
#pragma ADDRESS                can0ic_addr 009dH                /* CAN0 Interrupt Control Register*/
130
#pragma ADDRESS     int0ic_addr 009eH       /* INT0~ interrupt control register */
131
#pragma ADDRESS     rlvl_addr   009fH       /* Exit priority register */
132
#pragma ADDRESS     iio0ir_addr 00a0H       /* Interrupt request register 0 */
133
#pragma ADDRESS     iio1ir_addr 00a1H       /* Interrupt request register 1 */
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#pragma ADDRESS     iio2ir_addr 00a2H       /* Interrupt request register 2 */
135
#pragma ADDRESS     iio3ir_addr 00a3H       /* Interrupt request register 3 */
136
#pragma ADDRESS     iio4ir_addr 00a4H       /* Interrupt request register 4 */
137
#pragma ADDRESS     iio5ir_addr 00a5H       /* Interrupt request register 5 */
138
#pragma ADDRESS     iio6ir_addr 00a6H       /* Interrupt request register 6 */
139
#pragma ADDRESS     iio7ir_addr 00a7H       /* Interrupt request register 7 */
140
#pragma ADDRESS     iio8ir_addr 00a8H       /* Interrupt request register 8 */
141
#pragma ADDRESS     iio9ir_addr 00a9H       /* Interrupt request register 9 */
142
#pragma ADDRESS     iio10ir_addr 00aaH      /* Interrupt request register 10 */
143
#pragma ADDRESS     iio11ir_addr 00abH      /* Interrupt request register 11 */
144
#pragma ADDRESS     iio0ie_addr 00b0H       /* Interrupt enable register 0 */
145
#pragma ADDRESS     iio1ie_addr 00b1H       /* Interrupt enable register 1 */
146
#pragma ADDRESS     iio2ie_addr 00b2H       /* Interrupt enable register 2 */
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#pragma ADDRESS     iio3ie_addr 00b3H       /* Interrupt enable register 3 */
148
#pragma ADDRESS     iio4ie_addr 00b4H       /* Interrupt enable register 4 */
149
#pragma ADDRESS     iio5ie_addr 00b5H       /* Interrupt enable register 5 */
150
#pragma ADDRESS     iio6ie_addr 00b6H       /* Interrupt enable register 6 */
151
#pragma ADDRESS     iio7ie_addr 00b7H       /* Interrupt enable register 7 */
152
#pragma ADDRESS     iio8ie_addr 00b8H       /* Interrupt enable register 8 */
153
#pragma ADDRESS     iio9ie_addr 00b9H       /* Interrupt enable register 9 */
154
#pragma ADDRESS     iio10ie_addr 00baH      /* Interrupt enable register 10 */
155
#pragma ADDRESS     iio11ie_addr 00bbH      /* Interrupt enable register 11 */
156
#pragma ADDRESS     g0tm0_addr  00c0H       /* Group 0 time measurement register 0 */
157
#pragma ADDRESS     g0tm1_addr  00c2H       /* Group 0 time measurement register 1 */
158
#pragma ADDRESS     g0tm2_addr  00c4H       /* Group 0 time measurement register 2 */
159
#pragma ADDRESS     g0tm3_addr  00c6H       /* Group 0 time measurement register 3 */
160
#pragma ADDRESS     g0tm4_addr  00c8H       /* Group 0 time measurement register 4 */
161
#pragma ADDRESS     g0tm5_addr  00caH       /* Group 0 time measurement register 5 */
162
#pragma ADDRESS     g0tm6_addr  00ccH       /* Group 0 time measurement register 6 */
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#pragma ADDRESS     g0tm7_addr  00ceH       /* Group 0 time measurement register 7 */
164
#pragma ADDRESS     g0po0_addr  00c0H       /* Group 0 waveform generate register 0 */
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#pragma ADDRESS     g0po1_addr  00c2H       /* Group 0 waveform generate register 1 */
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#pragma ADDRESS     g0po2_addr  00c4H       /* Group 0 waveform generate register 2 */
167
#pragma ADDRESS     g0po3_addr  00c6H       /* Group 0 waveform generate register 3 */
168
#pragma ADDRESS     g0po4_addr  00c8H       /* Group 0 waveform generate register 4 */
169
#pragma ADDRESS     g0po5_addr  00caH       /* Group 0 waveform generate register 5 */
170
#pragma ADDRESS     g0po6_addr  00ccH       /* Group 0 waveform generate register 6 */
171
#pragma ADDRESS     g0po7_addr  00ceH       /* Group 0 waveform generate register 7 */
172
#pragma ADDRESS     g0pocr0_addr 00d0H      /* Group 0 pulse output control register0 */
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#pragma ADDRESS     g0pocr1_addr 00d1H      /* Group 0 pulse output control register1 */
174
#pragma ADDRESS     g0pocr2_addr 00d2H      /* Group 0 pulse output control register2 */
175
#pragma ADDRESS     g0pocr3_addr 00d3H      /* Group 0 pulse output control register3 */
176
#pragma ADDRESS     g0pocr4_addr 00d4H      /* Group 0 pulse output control register4 */
177
#pragma ADDRESS     g0pocr5_addr 00d5H      /* Group 0 pulse output control register5 */
178
#pragma ADDRESS     g0pocr6_addr 00d6H      /* Group 0 pulse output control register6 */
179
#pragma ADDRESS     g0pocr7_addr 00d7H      /* Group 0 pulse output control register7 */
180
#pragma ADDRESS     g0tmcr0_addr 00d8H      /* Group 0 time measuring control register0 */
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#pragma ADDRESS     g0tmcr1_addr 00d9H      /* Group 0 time measuring control register1 */
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#pragma ADDRESS     g0tmcr2_addr 00daH      /* Group 0 time measuring control register2 */
183
#pragma ADDRESS     g0tmcr3_addr 00dbH      /* Group 0 time measuring control register3 */
184
#pragma ADDRESS     g0tmcr4_addr 00dcH      /* Group 0 time measuring control register4 */
185
#pragma ADDRESS     g0tmcr5_addr 00ddH      /* Group 0 time measuring control register5 */
186
#pragma ADDRESS     g0tmcr6_addr 00deH      /* Group 0 time measuring control register6 */
187
#pragma ADDRESS     g0tmcr7_addr 00dfH      /* Group 0 time measuring control register7 */
188
#pragma ADDRESS     g0bt_addr   00e0H       /* Group 0 base timer register */
189
#pragma ADDRESS     g0bcr0_addr 00e2H       /* Group 0 base timer control register0 */
190
#pragma ADDRESS     g0bcr1_addr 00e3H       /* Group 0 base timer control register1 */
191
#pragma ADDRESS     g0tpr6_addr 00e4H       /* Group 0 priscale reload register6 */
192
#pragma ADDRESS     g0tpr7_addr 00e5H       /* Group 0 priscale reload register7 */
193
#pragma ADDRESS     g0fe_addr   00e6H       /* Group 0 function enable register */
194
#pragma ADDRESS     g0fs_addr   00e7H       /* Group 0 function select register */
195
#pragma ADDRESS     g0rb_addr   00e8H       /* Group 0 SI/O receive buffer register */
196
#pragma ADDRESS     g0tb_addr   00eaH       /* Group 0 SI/O transmitting buffer register */
197
#pragma ADDRESS     g0dr_addr   00eaH       /* Group 0 receive data register */
198
#pragma ADDRESS     g0ri_addr   00ecH       /* Group 0 receive input register */
199
#pragma ADDRESS     g0mr_addr   00edH       /* Group 0 SI/O communication control register */
200
#pragma ADDRESS     g0to_addr   00eeH       /* Group 0 transmit output register */
201
#pragma ADDRESS     g0cr_addr   00efH       /* Group 0 SI/O communication control register */
202
#pragma ADDRESS     g0cmp0_addr 00f0H       /* Group 0 data compare register 0 */
203
#pragma ADDRESS     g0cmp1_addr 00f1H       /* Group 0 data compare register 1 */
204
#pragma ADDRESS     g0cmp2_addr 00f2H       /* Group 0 data compare register 2 */
205
#pragma ADDRESS     g0cmp3_addr 00f3H       /* Group 0 data compare register 3 */
206
#pragma ADDRESS     g0msk0_addr 00f4H       /* Group 0 data mask register 0 */
207
#pragma ADDRESS     g0msk1_addr 00f5H       /* Group 0 data mask register 1 */
208
#pragma ADDRESS     g0rcrc_addr 00f8H       /* Group 0 receive CRC code register */
209
#pragma ADDRESS     g0tcrc_addr 00faH       /* Group 0 transmit CRC code register */
210
#pragma ADDRESS     g0emr_addr  00fcH       /* Group 0 SI/O expansion mode register */
211
#pragma ADDRESS     g0erc_addr  00fdH       /* Group 0 SI/O expansion receive control register */
212
#pragma ADDRESS     g0irf_addr  00feH       /* Group 0 SI/O special communication interrupt detect register */
213
#pragma ADDRESS     g0etc_addr  00ffH       /* Group 0 SI/O expansion transmit control register */
214
#pragma ADDRESS     g1tm0_addr  0100H       /* Group 1 time measurement register 0 */
215
#pragma ADDRESS                g1po0_addr        0100H                /* Group 1 waveform generate register 0 */
216
#pragma ADDRESS     g1tm1_addr  0102H       /* Group 1 time measurement register 1 */
217
#pragma ADDRESS                g1po1_addr        0102H                /* Group 1 waveform generate register 1 */
218
#pragma ADDRESS     g1tm2_addr  0104H       /* Group 1 time measurement register 2 */
219
#pragma ADDRESS                g1po2_addr        0104H                /* Group 1 waveform generate register 2 */
220
#pragma ADDRESS     g1tm3_addr  0106H       /* Group 1 time measurement register 3 */
221
#pragma ADDRESS                g1po3_addr        0106H                /* Group 1 waveform generate register 3 */
222
#pragma ADDRESS     g1tm4_addr  0108H       /* Group 1 time measurement register 4 */
223
#pragma ADDRESS                g1po4_addr        0108H                /* Group 1 waveform generate register 4 */
224
#pragma ADDRESS     g1tm5_addr  010aH       /* Group 1 time measurement register 5 */
225
#pragma ADDRESS                g1po5_addr        010aH                /* Group 1 waveform generate register 5 */
226
#pragma ADDRESS     g1tm6_addr  010cH       /* Group 1 time measurement register 6 */
227
#pragma ADDRESS                g1po6_addr        010cH                /* Group 1 waveform generate register 6 */
228
#pragma ADDRESS     g1tm7_addr  010eH       /* Group 1 time measurement register 7 */
229
#pragma ADDRESS                g1po7_addr        010eH                /* Group 1 waveform generate register 7 */
230
#pragma ADDRESS     g1pocr0_addr 0110H      /* Group 1 waveform generate control register 0 */
231
#pragma ADDRESS     g1pocr1_addr 0111H      /* Group 1 waveform generate control register 1 */
232
#pragma ADDRESS     g1pocr2_addr 0112H      /* Group 1 waveform generate control register 2 */
233
#pragma ADDRESS     g1pocr3_addr 0113H      /* Group 1 waveform generate control register 3 */
234
#pragma ADDRESS     g1pocr4_addr 0114H      /* Group 1 waveform generate control register 4 */
235
#pragma ADDRESS     g1pocr5_addr 0115H      /* Group 1 waveform generate control register 5 */
236
#pragma ADDRESS     g1pocr6_addr 0116H      /* Group 1 waveform generate control register 6 */
237
#pragma ADDRESS     g1pocr7_addr 0117H      /* Group 1 waveform generate control register 7 */
238
#pragma ADDRESS     g1tmcr0_addr 0118H      /* Group 1 time measurement control register 0 */
239
#pragma ADDRESS     g1tmcr1_addr 0119H      /* Group 1 time measurement control register 1 */
240
#pragma ADDRESS     g1tmcr2_addr 011aH      /* Group 1 time measurement control register 2 */
241
#pragma ADDRESS     g1tmcr3_addr 011bH      /* Group 1 time measurement control register 3 */
242
#pragma ADDRESS     g1tmcr4_addr 011cH      /* Group 1 time measurement control register 4 */
243
#pragma ADDRESS     g1tmcr5_addr 011dH      /* Group 1 time measurement control register 5 */
244
#pragma ADDRESS     g1tmcr6_addr 011eH      /* Group 1 time measurement control register 6 */
245
#pragma ADDRESS     g1tmcr7_addr 011fH      /* Group 1 time measurement control register 7 */
246
#pragma ADDRESS     g1bt_addr    0120H      /* Group 1 base timer register */
247
#pragma ADDRESS     g1bcr0_addr  0122H      /* Group 1 base timer control register 0 */
248
#pragma ADDRESS     g1bcr1_addr  0123H      /* Group 1 base timer control register 1 */
249
#pragma ADDRESS     g1tpr6_addr  0124H      /* Group 1 time measurement prescaler register 6 */
250
#pragma ADDRESS     g1tpr7_addr  0125H      /* Group 1 time measurement prescaler register 7 */
251
#pragma ADDRESS     g1fe_addr    0126H      /* Group 1 function enable register */
252
#pragma ADDRESS     g1fs_addr    0127H      /* Group 1 function select register */
253
#pragma ADDRESS     g1rb_addr    0128H      /* Group 1 SI/O communication buffer register */
254
#pragma ADDRESS     g1tb_addr    012aH      /* Group 1 SI/O transmiting data register */
255
#pragma ADDRESS     g1dr_addr    012aH      /* Group 1 receive data register */
256
#pragma ADDRESS     g1ri_addr    012cH      /* Group 1 receive input register */
257
#pragma ADDRESS     g1mr_addr    012dH      /* Group 1 SI/O communication mode register */
258
#pragma ADDRESS     g1to_addr    012eH      /* Group 1 transmit output register */
259
#pragma ADDRESS     g1cr_addr    012fH      /* Group 1 SI/O communication control register */
260
#pragma ADDRESS     g1cmp0_addr  0130H      /* Group 1 data compare register 0 */
261
#pragma ADDRESS     g1cmp1_addr  0131H      /* Group 1 data compare register 1 */
262
#pragma ADDRESS     g1cmp2_addr  0132H      /* Group 1 data compare register 2 */
263
#pragma ADDRESS     g1cmp3_addr  0133H      /* Group 1 data compare register 3 */
264
#pragma ADDRESS     g1msk0_addr  0134H      /* Group 1 data mask register 0 */
265
#pragma ADDRESS     g1msk1_addr  0135H      /* Group 1 data mask register 1 */
266
#pragma ADDRESS     g1rcrc_addr  0138H      /* Group 1 receive CRC code register */
267
#pragma ADDRESS     g1tcrc_addr  013aH      /* Group 1 transmit CRC code register */
268
#pragma ADDRESS     g1emr_addr   013cH      /* Group 1 SI/O expansion mode register */
269
#pragma ADDRESS     g1erc_addr   013dH      /* Group 1 SI/O expansion receive control register */
270
#pragma ADDRESS     g1irf_addr   013eH      /* Group 1 SI/O special communication interrupt detect register */
271
#pragma ADDRESS     g1etc_addr   013fH      /* Group 1 SI/O expansion transmit control register */
272
#pragma ADDRESS     g2po0_addr   0140H      /* Group 2 waveform generate register 0 */
273
#pragma ADDRESS     g2po1_addr   0142H      /* Group 2 waveform generate register 1 */
274
#pragma ADDRESS     g2po2_addr   0144H      /* Group 2 waveform generate register 2 */
275
#pragma ADDRESS     g2po3_addr   0146H      /* Group 2 waveform generate register 3 */
276
#pragma ADDRESS     g2po4_addr   0148H      /* Group 2 waveform generate register 4 */
277
#pragma ADDRESS     g2po5_addr   014aH      /* Group 2 waveform generate register 5 */
278
#pragma ADDRESS     g2po6_addr   014cH      /* Group 2 waveform generate register 6 */
279
#pragma ADDRESS     g2po7_addr   014eH      /* Group 2 waveform generate register 7 */
280
#pragma ADDRESS     g2pocr0_addr 0150H      /* Group 2 waveform generate control register 0 */
281
#pragma ADDRESS     g2pocr1_addr 0151H      /* Group 2 waveform generate control register 1 */
282
#pragma ADDRESS     g2pocr2_addr 0152H      /* Group 2 waveform generate control register 2 */
283
#pragma ADDRESS     g2pocr3_addr 0153H      /* Group 2 waveform generate control register 3 */
284
#pragma ADDRESS     g2pocr4_addr 0154H      /* Group 2 waveform generate control register 4 */
285
#pragma ADDRESS     g2pocr5_addr 0155H      /* Group 2 waveform generate control register 5 */
286
#pragma ADDRESS     g2pocr6_addr 0156H      /* Group 2 waveform generate control register 6 */
287
#pragma ADDRESS     g2pocr7_addr 0157H      /* Group 2 waveform generate control register 7 */
288
#pragma ADDRESS     g2bt_addr    0160H      /* Group 2 base timer register */
289
#pragma ADDRESS     g2bcr0_addr  0162H      /* Group 2 base timer control register 0 */
290
#pragma ADDRESS     g2bcr1_addr  0163H      /* Group 2 base timer control register 1 */
291
#pragma ADDRESS     btsr_addr    0164H      /* base timer start register */
292
#pragma ADDRESS     g2fe_addr    0166H      /* Group 2 function enable register */
293
#pragma ADDRESS     g2rtp_addr   0167H      /* Group 2 RTP output buffer register */
294
#pragma ADDRESS     g2mr_addr    016aH      /* Group 2 SI/O communication mode register */
295
#pragma ADDRESS     g2cr_addr    016bH      /* Group 2 SI/O communication control register */
296
#pragma ADDRESS     g2tb_addr    016cH      /* Group 2 SI/O transmit buffer register */
297
#pragma ADDRESS     g2rb_addr    016eH      /* Group 2 SI/O receive buffer register */
298
#pragma ADDRESS     iear_addr    0170H      /* Group 2 IEBus address register */
299
#pragma ADDRESS     iecr_addr    0172H      /* Group 2 IEBus control register */
300
#pragma ADDRESS     ietif_addr   0173H      /* Group 2 IEBus transmit interrupt cause detect register */
301
#pragma ADDRESS     ierif_addr   0174H      /* Group 2 IEBus receive interrupt cause detect register */
302
#pragma ADDRESS     ips_addr     0178H      /* Input function select register */
303
#pragma ADDRESS     g3mr_addr    017aH      /* Group 3 SI/O communication mode register */
304
#pragma ADDRESS     g3cr_addr    017bH      /* Group 3 SI/O communication control register */
305
#pragma ADDRESS     g3tb_addr    017cH      /* Group 3 SI/O transmit buffer register */
306
#pragma ADDRESS     g3rb_addr    017eH      /* Group 3 SI/O receive buffer register */
307
#pragma ADDRESS     g3po0_addr   0180H      /* Group 3 waveform generate register 0 */
308
#pragma ADDRESS     g3po1_addr   0182H      /* Group 3 waveform generate register 1 */
309
#pragma ADDRESS     g3po2_addr   0184H      /* Group 3 waveform generate register 2 */
310
#pragma ADDRESS     g3po3_addr   0186H      /* Group 3 waveform generate register 3 */
311
#pragma ADDRESS     g3po4_addr   0188H      /* Group 3 waveform generate register 4 */
312
#pragma ADDRESS     g3po5_addr   018aH      /* Group 3 waveform generate register 5 */
313
#pragma ADDRESS     g3po6_addr   018cH      /* Group 3 waveform generate register 6 */
314
#pragma ADDRESS     g3po7_addr   018eH      /* Group 3 waveform generate register 7 */
315
#pragma ADDRESS     g3pocr0_addr 0190H      /* Group 3 waveform generate control register 0 */
316
#pragma ADDRESS     g3pocr1_addr 0191H      /* Group 3 waveform generate control register 1 */
317
#pragma ADDRESS     g3pocr2_addr 0192H      /* Group 3 waveform generate control register 2 */
318
#pragma ADDRESS     g3pocr3_addr 0193H      /* Group 3 waveform generate control register 3 */
319
#pragma ADDRESS     g3pocr4_addr 0194H      /* Group 3 waveform generate control register 4 */
320
#pragma ADDRESS     g3pocr5_addr 0195H      /* Group 3 waveform generate control register 5 */
321
#pragma ADDRESS     g3pocr6_addr 0196H      /* Group 3 waveform generate control register 6 */
322
#pragma ADDRESS     g3pocr7_addr 0197H      /* Group 3 waveform generate control register 7 */
323
#pragma ADDRESS     g3mk4_addr   0198H      /* Group 3 waveform generate mask register 4 */
324
#pragma ADDRESS     g3mk5_addr   019aH      /* Group 3 waveform generate mask register 5 */
325
#pragma ADDRESS     g3mk6_addr   019cH      /* Group 3 waveform generate mask register 6 */
326
#pragma ADDRESS     g3mk7_addr   019eH      /* Group 3 waveform generate mask register 7 */
327
#pragma ADDRESS     g3bt_addr    01a0H      /* Group 3 base timer register */
328
#pragma ADDRESS     g3bcr0_addr  01a2H      /* Group 3 base timer control register 0 */
329
#pragma ADDRESS     g3bcr1_addr  01a3H      /* Group 3 base timer control register 1 */
330
#pragma ADDRESS     g3fe_addr    01a6H      /* Group 3 function enable register */
331
#pragma ADDRESS     g3rtp_addr   01a7H      /* Group 3 RTP output buffer register */
332
//#pragma ADDRESS                hdlc1_addr         01abH                /* Group 3 high-speed HDLC Communication Control Register 1 */
333
#pragma ADDRESS     hdlc_addr    01acH      /* Group 3 high-speed HDLC communication control register */
334
#pragma ADDRESS     g3flg_addr   01adH      /* Group 3 high-speed HDLC communication register */
335
#pragma ADDRESS     hcnt_addr    01aeH      /* Group 3 high-speed HDLC transmit counter */
336
#pragma ADDRESS     hadr0_addr         01b0H      /* Group 3 high-speed HDLC data compare register 0 */
337
#pragma ADDRESS     hmsk0_addr         01b2H      /* Group 3 high-speed HDLC data mask register 0 */
338
#pragma ADDRESS     hadr1_addr         01b4H      /* Group 3 high-speed HDLC data compare register 1 */
339
#pragma ADDRESS     hmsk1_addr         01b6H      /* Group 3 high-speed HDLC data mask register 1 */
340
#pragma ADDRESS     hadr2_addr         01b8H      /* Group 3 high-speed HDLC data compare register 2 */
341
#pragma ADDRESS     hmsk2_addr         01baH      /* Group 3 high-speed HDLC data mask register 2 */
342
#pragma ADDRESS     hadr3_addr         01bcH      /* Group 3 high-speed HDLC data compare register 3 */
343
#pragma ADDRESS     hmsk3_addr          01beH      /* Group 3 high-speed HDLC data mask register 3 */
344
345
#pragma ADDRESS     ad10_addr    01c0H      /* A/D1 register 0 */
346
#pragma ADDRESS     ad11_addr    01c2H      /* A/D1 register 1 */
347
#pragma ADDRESS     ad12_addr    01c4H      /* A/D1 register 2 */
348
#pragma ADDRESS     ad13_addr    01c6H      /* A/D1 register 3 */
349
#pragma ADDRESS     ad14_addr    01c8H      /* A/D1 register 4 */
350
#pragma ADDRESS     ad15_addr    01caH      /* A/D1 register 5 */
351
#pragma ADDRESS     ad16_addr    01ccH      /* A/D1 register 6 */
352
#pragma ADDRESS     ad17_addr    01ceH      /* A/D1 register 7 */
353
#pragma ADDRESS     ad1con2_addr 01d4H      /* A/D1 control register 2 */
354
#pragma ADDRESS     ad1con0_addr 01d6H      /* A/D1 control register 0 */
355
#pragma ADDRESS     ad1con1_addr 01d7H      /* A/D1 control register 1 */
356
357
#pragma ADDRESS                c0slot0_0_addr        01e0H        /* Can0 Messege Slot Buffer0 Data0 */
358
#pragma ADDRESS                c0slot0_1_addr        01e1H        /* Can0 Messege Slot Buffer0 Data1 */
359
#pragma ADDRESS                c0slot0_2_addr        01e2H        /* Can0 Messege Slot Buffer0 Data2 */
360
#pragma ADDRESS                c0slot0_3_addr        01e3H        /* Can0 Messege Slot Buffer0 Data3 */
361
#pragma ADDRESS                c0slot0_4_addr        01e4H        /* Can0 Messege Slot Buffer0 Data4 */
362
#pragma ADDRESS                c0slot0_5_addr        01e5H        /* Can0 Messege Slot Buffer0 Data5 */
363
#pragma ADDRESS                c0slot0_6_addr        01e6H        /* Can0 Messege Slot Buffer0 Data6 */
364
#pragma ADDRESS                c0slot0_7_addr        01e7H        /* Can0 Messege Slot Buffer0 Data7 */
365
#pragma ADDRESS                c0slot0_8_addr        01e8H        /* Can0 Messege Slot Buffer0 Data8 */
366
#pragma ADDRESS                c0slot0_9_addr        01e9H        /* Can0 Messege Slot Buffer0 Data9 */
367
#pragma ADDRESS                c0slot0_10_addr        01eaH        /* Can0 Messege Slot Buffer0 Data10 */
368
#pragma ADDRESS                c0slot0_11_addr        01ebH        /* Can0 Messege Slot Buffer0 Data11 */
369
#pragma ADDRESS                c0slot0_12_addr        01ecH        /* Can0 Messege Slot Buffer0 Data12 */
370
#pragma ADDRESS                c0slot0_13_addr        01edH        /* Can0 Messege Slot Buffer0 Data13 */
371
#pragma ADDRESS                c0slot0_14_addr        01eeH        /* Can0 Messege Slot Buffer0 Data14 */
372
#pragma ADDRESS                c0slot0_15_addr        01efH        /* Can0 Messege Slot Buffer0 Data15 */
373
#pragma ADDRESS                c0slot1_0_addr        01f0H        /* Can0 Messege Slot Buffer1 Data0 */
374
#pragma ADDRESS                c0slot1_1_addr        01f1H        /* Can0 Messege Slot Buffer1 Data1 */
375
#pragma ADDRESS                c0slot1_2_addr        01f2H        /* Can0 Messege Slot Buffer1 Data2 */
376
#pragma ADDRESS                c0slot1_3_addr        01f3H        /* Can0 Messege Slot Buffer1 Data3 */
377
#pragma ADDRESS                c0slot1_4_addr        01f4H        /* Can0 Messege Slot Buffer1 Data4 */
378
#pragma ADDRESS                c0slot1_5_addr        01f5H        /* Can0 Messege Slot Buffer1 Data5 */
379
#pragma ADDRESS                c0slot1_6_addr        01f6H        /* Can0 Messege Slot Buffer1 Data6 */
380
#pragma ADDRESS                c0slot1_7_addr        01f7H        /* Can0 Messege Slot Buffer1 Data7 */
381
#pragma ADDRESS                c0slot1_8_addr        01f8H        /* Can0 Messege Slot Buffer1 Data8 */
382
#pragma ADDRESS                c0slot1_9_addr        01f9H        /* Can0 Messege Slot Buffer1 Data9 */
383
#pragma ADDRESS                c0slot1_10_addr        01faH        /* Can0 Messege Slot Buffer1 Data10 */
384
#pragma ADDRESS                c0slot1_11_addr        01fbH        /* Can0 Messege Slot Buffer1 Data11 */
385
#pragma ADDRESS                c0slot1_12_addr        01fcH        /* Can0 Messege Slot Buffer1 Data12 */
386
#pragma ADDRESS                c0slot1_13_addr        01fdH        /* Can0 Messege Slot Buffer1 Data13 */
387
#pragma ADDRESS                c0slot1_14_addr        01feH        /* Can0 Messege Slot Buffer1 Data14 */
388
#pragma ADDRESS                c0slot1_15_addr        01ffH        /* Can0 Messege Slot Buffer1 Data15 */
389
#pragma ADDRESS                c0ctlr0_addr        0200H        /* Can0 Status Register */
390
#pragma ADDRESS                c0str_addr                0202H        /* Can0 Status Register */
391
#pragma ADDRESS                c0idr_addr                0204H        /* Can0 Extended ID Register */
392
#pragma ADDRESS                c0conr_addr                0206H        /* Can0 Configration Register */
393
#pragma ADDRESS                c0tsr_addr                0208H        /* Can0 Time Stamp Register */
394
#pragma ADDRESS                c0tec_addr                020aH        /* Can0 Transmit Error Count Register */
395
#pragma ADDRESS                c0rec_addr                020bH        /* Can0 Receive Error Count Register */
396
#pragma ADDRESS                c0sistr_addr        020cH        /* Can0 Slot Interrupt Status Register        */
397
#pragma ADDRESS                c0simkr_addr        0210H        /* Can0 Slot Interrupt Mask Register */
398
#pragma ADDRESS                c0eimkr_addr        0214H        /* Can0 Error Interrupt Mask Register */
399
#pragma ADDRESS                c0eistr_addr        0215H        /* Can0 Error Interrupt Status Register */
400
#pragma ADDRESS                c0brp_addr                0217H        /* Can0 Baud Rate Prescaler */
401
#pragma ADDRESS                c0gmr0_addr                0228H        /* Can0 Global Mask Register Standard ID0 */
402
#pragma ADDRESS                c0gmr1_addr                0229H        /* Can0 Global Mask Register Standard ID1 */
403
#pragma ADDRESS                c0gmr2_addr                022aH        /* Can0 Global Mask Register Extended ID0 */
404
#pragma ADDRESS                c0gmr3_addr                022bH        /* Can0 Global Mask Register Extended ID1 */
405
#pragma ADDRESS                c0gmr4_addr                022cH        /* Can0 Global Mask Register Extended ID2 */
406
#pragma ADDRESS                c0mctl0_addr        0230H        /* Can0 Messege Slot0 Control Register */
407
#pragma ADDRESS                c0lmar0_addr        0230H        /* Can0 Local Mask RegisterA Standard ID0 */
408
#pragma ADDRESS                c0mctl1_addr        0231H        /* Can0 Messege Slot1 Control Register */
409
#pragma ADDRESS                c0lmar1_addr        0231H        /* Can0 Local Mask RegisterA Standard ID1 */
410
#pragma ADDRESS                c0mctl2_addr        0232H        /* Can0 Messege Slot2 Control Register */
411
#pragma ADDRESS                c0lmar2_addr        0232H        /* Can0 Local Mask RegisterA Extended ID0 */
412
#pragma ADDRESS                c0mctl3_addr        0233H        /* Can0 Messege Slot3 Control Register        */
413
#pragma ADDRESS                c0lmar3_addr        0233H        /* Can0 Local Mask RegisterA Extended ID1 */
414
#pragma ADDRESS                c0mctl4_addr        0234H        /* Can0 Messege Slot4 Control Register        */
415
#pragma ADDRESS                c0lmar4_addr        0234H        /* Can0 Local Mask RegisterA Extended ID2 */
416
#pragma ADDRESS                c0mctl5_addr        0235H        /* Can0 Messege Slot5 Control Register        */
417
#pragma ADDRESS                c0mctl6_addr        0236H        /* Can0 Messege Slot6 Control Register        */
418
#pragma ADDRESS                c0mctl7_addr        0237H        /* Can0 Messege Slot7 Control Register        */
419
#pragma ADDRESS                c0mctl8_addr        0238H        /* Can0 Messege Slot8 Control Register        */
420
#pragma ADDRESS                c0lmbr0_addr        0238H        /* Can0 Local Mask RegisterB Standard ID0 */
421
#pragma ADDRESS                c0mctl9_addr        0239H        /* Can0 Messege Slot9 Control Register        */
422
#pragma ADDRESS                c0lmbr1_addr        0239H        /* Can0 Local Mask RegisterB Standard ID1 */
423
#pragma ADDRESS                c0mctl10_addr        023aH        /* Can0 Messege Slot10 Control Register */
424
#pragma ADDRESS                c0lmbr2_addr        023aH        /* Can0 Local Mask RegisterB Extended ID2 */
425
#pragma ADDRESS                c0mctl11_addr        023bH        /* Can0 Messege Slot11 Control Register */
426
#pragma ADDRESS                c0lmbr3_addr        023bH        /* Can0 Local Mask RegisterB Extended ID3 */
427
#pragma ADDRESS                c0mctl12_addr        023cH        /* Can0 Messege Slot12 Control Register */
428
#pragma ADDRESS                c0lmbr4_addr        023cH        /* Can0 Local Mask RegisterB Extended ID4 */
429
#pragma ADDRESS                c0mctl13_addr        023dH        /* Can0 Messege Slot13 Control Register */
430
#pragma ADDRESS                c0mctl14_addr        023eH        /* Can0 Messege Slot14 Control Register */
431
#pragma ADDRESS                c0mctl15_addr        023fH        /* Can0 Messege Slot15 Control Register */
432
#pragma ADDRESS                c0sbs_addr                0240H        /* Can0 Slot Buffer Select Register */
433
#pragma ADDRESS                c0ctlr1_addr                0241H        /* Can0 Control Register 1        */
434
#pragma ADDRESS                c0slpr_addr                0242H        /* Can0 Clock Stop Control Register */
435
#pragma ADDRESS                c0afs_addr                0244H        /* Can0 Acceptance Filtering Support Unit */
436
437
#pragma ADDRESS     x0r_addr    02c0H       /* X0 register */
438
#pragma ADDRESS     y0r_addr    02c0H       /* Y0 register */
439
#pragma ADDRESS     x1r_addr    02c2H       /* X1 register */
440
#pragma ADDRESS     y1r_addr    02c2H       /* Y1 register */
441
#pragma ADDRESS     x2r_addr    02c4H       /* X2 register */
442
#pragma ADDRESS     y2r_addr    02c4H       /* Y2 register */
443
#pragma ADDRESS     x3r_addr    02c6H       /* X3 register */
444
#pragma ADDRESS     y3r_addr    02c6H       /* Y3 register */
445
#pragma ADDRESS     x4r_addr    02c8H       /* X4 register */
446
#pragma ADDRESS     y4r_addr    02c8H       /* Y4 register */
447
#pragma ADDRESS     x5r_addr    02caH       /* X5 register */
448
#pragma ADDRESS     y5r_addr    02caH       /* Y5 register */
449
#pragma ADDRESS     x6r_addr    02ccH       /* X6 register */
450
#pragma ADDRESS     y6r_addr    02ccH       /* Y6 register */
451
#pragma ADDRESS     x7r_addr    02ceH       /* X7 register */
452
#pragma ADDRESS     y7r_addr    02ceH       /* Y7 register */
453
#pragma ADDRESS     x8r_addr    02d0H       /* X8 register */
454
#pragma ADDRESS     y8r_addr    02d0H       /* Y8 register */
455
#pragma ADDRESS     x9r_addr    02d2H       /* X9 register */
456
#pragma ADDRESS     y9r_addr    02d2H       /* Y9 register */
457
#pragma ADDRESS     x10r_addr   02d4H       /* X10 register */
458
#pragma ADDRESS     y10r_addr   02d4H       /* Y10 register */
459
#pragma ADDRESS     x11r_addr   02d6H       /* X11 register */
460
#pragma ADDRESS     y11r_addr   02d6H       /* Y11 register */
461
#pragma ADDRESS     x12r_addr   02d8H       /* X12 register */
462
#pragma ADDRESS     y12r_addr   02d8H       /* Y12 register */
463
#pragma ADDRESS     x13r_addr   02daH       /* X13 register */
464
#pragma ADDRESS     y13r_addr   02daH       /* Y13 register */
465
#pragma ADDRESS     x14r_addr   02dcH       /* X14 register */
466
#pragma ADDRESS     y14r_addr   02dcH       /* Y14 register */
467
#pragma ADDRESS     x15r_addr   02deH       /* X15 register */
468
#pragma ADDRESS     y15r_addr   02deH       /* Y15 register */
469
#pragma ADDRESS     xyc_addr    02e0H       /* X-Y control register */
470
471
#pragma ADDRESS     u1smr4_addr 02e4H       /* UART1 special mode register 4 */
472
#pragma ADDRESS     u1smr3_addr 02e5H       /* UART1 special mode register 3 */
473
#pragma ADDRESS     u1smr2_addr 02e6H       /* UART1 special mode register 2 */
474
#pragma ADDRESS     u1smr_addr  02e7H       /* UART1 special mode register */
475
#pragma ADDRESS     u1mr_addr   02e8H       /* UART1 transmit/receive mode register */
476
#pragma ADDRESS     u1brg_addr  02e9H       /* UART1 bit rate generator */
477
#pragma ADDRESS     u1tb_addr   02eaH       /* UART1 transmit buffer register */
478
#pragma ADDRESS     u1c0_addr   02ecH       /* UART1 transmit/receive control register 0 */
479
#pragma ADDRESS     u1c1_addr   02edH       /* UART1 transmit/receive control register 1 */
480
#pragma ADDRESS     u1rb_addr   02eeH       /* UART1 receive buffer register */
481
482
#pragma ADDRESS     u4smr4_addr 02f4H       /* UART4 special mode register 4 */
483
#pragma ADDRESS     u4smr3_addr 02f5H       /* UART4 special mode register 3 */
484
#pragma ADDRESS     u4smr2_addr 02f6H       /* UART4 special mode register 2 */
485
#pragma ADDRESS     u4smr_addr  02f7H       /* UART4 special mode register */
486
#pragma ADDRESS     u4mr_addr   02f8H       /* UART4 transmit/receive mode register */
487
#pragma ADDRESS     u4brg_addr  02f9H       /* UART4 bit rate generator */
488
#pragma ADDRESS     u4tb_addr   02faH       /* UART4 transmit buffer register */
489
#pragma ADDRESS     u4c0_addr   02fcH       /* UART4 transmit/receive control register 0 */
490
#pragma ADDRESS     u4c1_addr   02fdH       /* UART4 transmit/receive control register 1 */
491
#pragma ADDRESS     u4rb_addr   02feH       /* UART4 receive buffer register */
492
493
#pragma ADDRESS     tbsr_addr   0300H       /* Timer B3,4,5 count start flag */
494
#pragma ADDRESS     ta11_addr   0302H       /* Timer A1-1 register */
495
#pragma ADDRESS     ta21_addr   0304H       /* Timer A2-1 register */
496
#pragma ADDRESS     ta41_addr   0306H       /* Timer A4-1 register */
497
#pragma ADDRESS     invc0_addr  0308H       /* Three-phase PWM control regester 0 */
498
#pragma ADDRESS     invc1_addr  0309H       /* Three-phase PWM control register 1 */
499
#pragma ADDRESS     idb0_addr   030aH       /* Three-phase output buffer register 0 */
500
#pragma ADDRESS     idb1_addr   030bH       /* Three-phase output buffer register 1 */
501
#pragma ADDRESS     dtt_addr    030cH       /* Dead time timer */
502
#pragma ADDRESS     ictb2_addr  030dH       /* Timer B2 interrupt occurences frequency set counter */
503
#pragma ADDRESS     tb3_addr    0310H       /* Timer B3 register */
504
#pragma ADDRESS     tb4_addr    0312H       /* Timer B4 register */
505
#pragma ADDRESS     tb5_addr    0314H       /* Timer B5 register */
506
#pragma ADDRESS     tb3mr_addr  031bH       /* Timer B3 mode register */
507
#pragma ADDRESS     tb4mr_addr  031cH       /* Timer B4 mode register */
508
#pragma ADDRESS     tb5mr_addr  031dH       /* Timer B5 mode register */
509
#pragma ADDRESS     ifsr_addr   031fH       /* Interrupt cause select register */
510
511
#pragma ADDRESS     u3smr4_addr 0324H       /* UART3 special mode register 4 */
512
#pragma ADDRESS     u3smr3_addr 0325H       /* UART3 special mode register 3 */
513
#pragma ADDRESS     u3smr2_addr 0326H       /* UART3 special mode register 2 */
514
#pragma ADDRESS     u3smr_addr  0327H       /* UART3 special mode register */
515
#pragma ADDRESS     u3mr_addr   0328H       /* UART3 transmit/receive mode register */
516
#pragma ADDRESS     u3brg_addr  0329H       /* UART3 bit rate generator */
517
#pragma ADDRESS     u3tb_addr   032aH       /* UART3 transmit buffer register */
518
#pragma ADDRESS     u3c0_addr   032cH       /* UART3 transmit/receive control register 0 */
519
#pragma ADDRESS     u3c1_addr   032dH       /* UART3 transmit/receive control register 1 */
520
#pragma ADDRESS     u3rb_addr   032eH       /* UART3 receive buffer register */
521
#pragma ADDRESS     u2smr4_addr 0334H       /* UART2 special mode register 4 */
522
#pragma ADDRESS     u2smr3_addr 0335H       /* UART2 special mode register 3 */
523
#pragma ADDRESS     u2smr2_addr 0336H       /* UART2 special mode register 2 */
524
#pragma ADDRESS     u2smr_addr  0337H       /* UART2 special mode register */
525
#pragma ADDRESS     u2mr_addr   0338H       /* UART2 transmit/receive mode register */
526
#pragma ADDRESS     u2brg_addr  0339H       /* UART2 bit rate generator */
527
#pragma ADDRESS     u2tb_addr   033aH       /* UART2 transmit buffer register */
528
#pragma ADDRESS     u2c0_addr   033cH       /* UART2 transmit/receive control register 0 */
529
#pragma ADDRESS     u2c1_addr   033dH       /* UART2 transmit/receive control register 1 */
530
#pragma ADDRESS     u2rb_addr   033eH       /* UART2 receive buffer register */
531
532
#pragma ADDRESS     tabsr_addr  0340H       /* Count start flag */
533
#pragma ADDRESS     cpsrf_addr  0341H       /* Clock prescaler reset flag */
534
#pragma ADDRESS     onsf_addr   0342H       /* One-shot start flag */
535
#pragma ADDRESS     trgsr_addr  0343H       /* Trigger select register */
536
#pragma ADDRESS     udf_addr    0344H       /* Up/down flag */
537
#pragma ADDRESS     ta0_addr    0346H       /* Timer A0 register */
538
#pragma ADDRESS     ta1_addr    0348H       /* Timer A1 register */
539
#pragma ADDRESS     ta2_addr    034aH       /* Timer A2 register */
540
#pragma ADDRESS     ta3_addr    034cH       /* Timer A3 register */
541
#pragma ADDRESS     ta4_addr    034eH       /* Timer A4 register */
542
#pragma ADDRESS     tb0_addr    0350H       /* Timer B0 register */
543
#pragma ADDRESS     tb1_addr    0352H       /* Timer B1 register */
544
#pragma ADDRESS     tb2_addr    0354H       /* Timer B2 register */
545
#pragma ADDRESS     ta0mr_addr  0356H       /* Timer A0 mode register */
546
#pragma ADDRESS     ta1mr_addr  0357H       /* Timer A1 mode register */
547
#pragma ADDRESS     ta2mr_addr  0358H       /* Timer A2 mode register */
548
#pragma ADDRESS     ta3mr_addr  0359H       /* Timer A3 mode register */
549
#pragma ADDRESS     ta4mr_addr  035aH       /* Timer A4 mode register */
550
#pragma ADDRESS     tb0mr_addr  035bH       /* Timer B0 mode register */
551
#pragma ADDRESS     tb1mr_addr  035cH       /* Timer B1 mode register */
552
#pragma ADDRESS     tb2mr_addr  035dH       /* Timer B2 mode register */
553
#pragma ADDRESS     tb2sc_addr  035eH       /* Timer B2 special mode register */
554
#pragma ADDRESS     tcspr_addr  035fH       /* Count source prescaler register */
555
556
#pragma ADDRESS     u0smr4_addr 0364H       /* UART0 special mode register 4 */
557
#pragma ADDRESS     u0smr3_addr 0365H       /* UART0 special mode register 3 */
558
#pragma ADDRESS     u0smr2_addr 0366H       /* UART0 special mode register 2 */
559
#pragma ADDRESS     u0smr_addr  0367H       /* UART0 special mode register */
560
#pragma ADDRESS     u0mr_addr   0368H       /* UART0 transmit/receive mode register */
561
#pragma ADDRESS     u0brg_addr  0369H       /* UART0 bit rate generator */
562
#pragma ADDRESS     u0tb_addr   036aH       /* UART0 transmit buffer register */
563
#pragma ADDRESS     u0c0_addr   036cH       /* UART0 transmit/receive control register 0 */
564
#pragma ADDRESS     u0c1_addr   036dH       /* UART0 transmit/receive control register 1 */
565
#pragma ADDRESS     u0rb_addr   036eH       /* UART0 receive buffer register */
566
#pragma ADDRESS     plc0_addr   0376H       /* PLL control register 0 */
567
#pragma ADDRESS     plc1_addr   0377H       /* PLL control register 1 */
568
#pragma ADDRESS     dm0sl_addr  0378H       /* DMA0 cause select register */
569
#pragma ADDRESS     dm1sl_addr  0379H       /* DMA1 cause select register */
570
#pragma ADDRESS     dm2sl_addr  037aH       /* DMA1 cause select register */
571
#pragma ADDRESS     dm3sl_addr  037bH       /* DMA1 cause select register */
572
#pragma ADDRESS     crcd_addr   037cH       /* CRC data register */
573
#pragma ADDRESS     crcin_addr  037eH       /* CRC input register */
574
#pragma ADDRESS     ad00_addr   0380H       /* A/D0 register 0 */
575
#pragma ADDRESS     ad01_addr   0382H       /* A/D0 register 1 */
576
#pragma ADDRESS     ad02_addr   0384H       /* A/D0 register 2 */
577
#pragma ADDRESS     ad03_addr   0386H       /* A/D0 register 3 */
578
#pragma ADDRESS     ad04_addr   0388H       /* A/D0 register 4 */
579
#pragma ADDRESS     ad05_addr   038aH       /* A/D0 register 5 */
580
#pragma ADDRESS     ad06_addr   038cH       /* A/D0 register 6 */
581
#pragma ADDRESS     ad07_addr   038eH       /* A/D0 register 7 */
582
#pragma ADDRESS     ad0con2_addr 0394H      /* A/D0 control register 2 */
583
#pragma ADDRESS     ad0con0_addr 0396H      /* A/D0 control register 0 */
584
#pragma ADDRESS     ad0con1_addr 0397H      /* A/D0 control register 1 */
585
#pragma ADDRESS     da0_addr    0398H       /* D/A register 0 */
586
#pragma ADDRESS     da1_addr    039aH       /* D/A register 1 */
587
#pragma ADDRESS     dacon_addr  039cH       /* D/A control register */
588
589
#pragma ADDRESS     ps8_addr    03a0H       /* Function select register A8 */
590
#pragma ADDRESS     ps9_addr    03a1H       /* Function select register A9 */
591
592
#pragma ADDRESS     psc_addr    03afH       /* Function select register C */
593
#pragma ADDRESS     ps0_addr    03b0H       /* Function select register A0 */
594
#pragma ADDRESS     ps1_addr    03b1H       /* Function select register A1 */
595
#pragma ADDRESS     psl0_addr   03b2H       /* Function select register B0 */
596
#pragma ADDRESS     psl1_addr   03b3H       /* Function select register B1 */
597
#pragma ADDRESS     ps2_addr    03b4H       /* Function select register A2 */
598
#pragma ADDRESS     ps3_addr    03b5H       /* Function select register A3 */
599
#pragma ADDRESS     psl2_addr   03b6H       /* Function select register B2 */
600
#pragma ADDRESS     psl3_addr   03b7H       /* Function select register B3 */
601
602
#pragma ADDRESS     ps5_addr    03b9H       /* Function select register A5 */
603
604
#pragma ADDRESS     ps6_addr    03bcH       /* Function select register A6 */
605
#pragma ADDRESS     ps7_addr    03bdH       /* Function select register A7 */
606
607
#pragma ADDRESS     p6_addr     03c0H       /* Port P6 register */
608
#pragma ADDRESS     p7_addr     03c1H       /* Port P7 register */
609
#pragma ADDRESS     pd6_addr    03c2H       /* Port P6 direction register */
610
#pragma ADDRESS     pd7_addr    03c3H       /* Port P7 direction register */
611
#pragma ADDRESS     p8_addr     03c4H       /* Port P8 register */
612
#pragma ADDRESS     p9_addr     03c5H       /* Port P9 register */
613
#pragma ADDRESS     pd8_addr    03c6H       /* Port P8 direction register */
614
#pragma ADDRESS     pd9_addr    03c7H       /* Port P9 direction register */
615
#pragma ADDRESS     p10_addr    03c8H       /* Port P10 register */
616
#pragma ADDRESS     p11_addr    03c9H       /* Port P11 register */
617
#pragma ADDRESS     pd10_addr   03caH       /* Port P10 direction register */
618
#pragma ADDRESS     pd11_addr   03cbH       /* Port P11 direction register */
619
#pragma ADDRESS     p12_addr    03ccH       /* Port P12 register */
620
#pragma ADDRESS     p13_addr    03cdH       /* Port P13 register */
621
#pragma ADDRESS     pd12_addr   03ceH       /* Port P12 direction register */
622
#pragma ADDRESS     pd13_addr   03cfH       /* Port P13 direction register */
623
#pragma ADDRESS     p14_addr    03d0H       /* Port P14 register */
624
#pragma ADDRESS     p15_addr    03d1H       /* Port P15 register */
625
#pragma ADDRESS     pd14_addr   03d2H       /* Port P14 direction register */
626
#pragma ADDRESS     pd15_addr   03d3H       /* Port P15 direction register */
627
#pragma ADDRESS     pur2_addr   03daH       /* Pull-up control register 2 */
628
#pragma ADDRESS     pur3_addr   03dbH       /* Pull-up control register 3 */
629
#pragma ADDRESS     pur4_addr   03dcH       /* Pull-up control register 4 */
630
#pragma ADDRESS     p0_addr     03e0H       /* Port P0 register */
631
#pragma ADDRESS     p1_addr     03e1H       /* Port P1 register */
632
#pragma ADDRESS     pd0_addr    03e2H       /* Port P0 direction register */
633
#pragma ADDRESS     pd1_addr    03e3H       /* Port P1 direction register */
634
#pragma ADDRESS     p2_addr     03e4H       /* Port P2 register */
635
#pragma ADDRESS     p3_addr     03e5H       /* Port P3 register */
636
#pragma ADDRESS     pd2_addr    03e6H       /* Port P2 direction register */
637
#pragma ADDRESS     pd3_addr    03e7H       /* Port P3 direction register */
638
#pragma ADDRESS     p4_addr     03e8H       /* Port P4 register */
639
#pragma ADDRESS     p5_addr     03e9H       /* Port P5 register */
640
#pragma ADDRESS     pd4_addr    03eaH       /* Port P4 direction register */
641
#pragma ADDRESS     pd5_addr    03ebH       /* Port P5 direction register */
642
#pragma ADDRESS     pur0_addr   03f0H       /* Pull-up control register 0 */
643
#pragma ADDRESS     pur1_addr   03f1H       /* Pull-up control register 1 */
644
#pragma ADDRESS     pcr_addr    03ffH       /* Port control register */
645
/*******************************************************
646
*   declare  SFR char                                   *
647
********************************************************/
648
unsigned char   da0_addr;               /* D/A register 0 */
649
#define     da0     da0_addr
650
651
unsigned char   da1_addr;               /* D/A register 1 */
652
#define     da1     da1_addr
653
654
/********************************************************
655
*   declare  SFR short                                  *
656
********************************************************/
657
/*---------------------------------------------------------------------
658
    Timer registers ; Read and write to this register in 16-bit units.
659
-----------------------------------------------------------------------*/
660
unsigned short   ta11_addr;             /* Timer A1-1 register */
661
#define     ta11     ta11_addr
662
663
unsigned short   ta21_addr;             /* Timer A2-1 register */
664
#define     ta21     ta21_addr
665
666
unsigned short   ta41_addr;             /* Timer A4-1 register */
667
#define     ta41     ta41_addr
668
669
unsigned short   tb3_addr;              /* Timer B3 register */
670
#define     tb3     tb3_addr
671
672
unsigned short   tb4_addr;              /* Timer B4 register */
673
#define     tb4     tb4_addr
674
675
unsigned short   tb5_addr;              /* Timer B5 register */
676
#define     tb5     tb5_addr
677
678
unsigned short   ta0_addr;              /* Timer A0 register */
679
#define     ta0     ta0_addr
680
681
unsigned short   ta1_addr;              /* Timer A1 register */
682
#define     ta1     ta1_addr
683
684
unsigned short   ta2_addr;              /* Timer A2 register */
685
#define     ta2     ta2_addr
686
687
unsigned short   ta3_addr;              /* Timer A3 register */
688
#define     ta3     ta3_addr
689
690
unsigned short   ta4_addr;              /* Timer A4 register */
691
#define     ta4     ta4_addr
692
693
unsigned short   tb0_addr;              /* Timer B0 register */
694
#define     tb0     tb0_addr
695
696
unsigned short   tb1_addr;              /* Timer B1 register */
697
#define     tb1     tb1_addr
698
699
unsigned short   tb2_addr;              /* Timer B2 register */
700
#define     tb2     tb2_addr
701
702
/*---------------------------------------------------------------------
703
    IIO registers ; Read and write to this register in 16-bit units.
704
-----------------------------------------------------------------------*/
705
union{
706
    struct{
707
        char    low;                /* Low  8 bit */
708
        char    high;               /* High 8 bit */
709
    }byte;
710
    unsigned short  word;
711
}g0bt_addr,g1bt_addr,
712
 g0tm0_addr,g0tm1_addr,g0tm2_addr,g0tm3_addr,g0tm4_addr,g0tm5_addr,g0tm6_addr,g0tm7_addr,
713
 g1tm0_addr,g1tm1_addr,g1tm2_addr,g1tm3_addr,g1tm4_addr,g1tm5_addr,g1tm6_addr,g1tm7_addr,
714
 g0po0_addr,g0po1_addr,g0po2_addr,g0po3_addr,g0po4_addr,g0po5_addr,g0po6_addr,g0po7_addr,
715
 g1po0_addr,g1po1_addr,g1po2_addr,g1po3_addr,g1po4_addr,g1po5_addr,g1po6_addr,g1po7_addr,
716
 g0tcrc_addr,g1tcrc_addr,g0rcrc_addr,g1rcrc_addr,
717
 g2bt_addr,
718
 g2po0_addr,g2po1_addr,g2po2_addr,g2po3_addr,g2po4_addr,g2po5_addr,g2po6_addr,g2po7_addr,
719
 iear_addr,
720
 g3bt_addr,
721
 g3po0_addr,g3po1_addr,g3po2_addr,g3po3_addr,g3po4_addr,g3po5_addr,g3po6_addr,g3po7_addr,
722
 g3mk4_addr,g3mk5_addr,g3mk6_addr,g3mk7_addr,
723
 g3tb_addr,g3rb_addr,hcnt_addr,hadr0_addr,hadr1_addr,hadr2_addr,hadr3_addr,
724
 hmsk0_addr,hmsk1_addr,hmsk2_addr,hmsk3_addr;
725
726
/********************************************************
727
*   group 0 and 1                                       *
728
********************************************************/
729
#define     g0bt        g0bt_addr.word      /* Group 0 base timer register */
730
#define     g0btl       g0bt_addr.byte.low
731
#define     g0bth       g0bt_addr.byte.high
732
733
#define     g1bt        g1bt_addr.word      /* Group 1 base timer register */
734
#define     g1btl       g1bt_addr.byte.low
735
#define     g1bth       g1bt_addr.byte.high
736
737
#define     g0tm0        g0tm0_addr.word      /* Group 0 time measurement register 0 */
738
#define     g0tm0l       g0tm0_addr.byte.low
739
#define     g0tm0h       g0tm0_addr.byte.high
740
741
#define     g0tm1        g0tm1_addr.word      /* Group 0 time measurement register 1 */
742
#define     g0tm1l       g0tm1_addr.byte.low
743
#define     g0tm1h       g0tm1_addr.byte.high
744
745
#define     g0tm2        g0tm2_addr.word      /* Group 0 time measurement register 2 */
746
#define     g0tm2l       g0tm2_addr.byte.low
747
#define     g0tm2h       g0tm2_addr.byte.high
748
749
#define     g0tm3        g0tm3_addr.word      /* Group 0 time measurement register 3 */
750
#define     g0tm3l       g0tm3_addr.byte.low
751
#define     g0tm3h       g0tm3_addr.byte.high
752
753
#define     g0tm4        g0tm4_addr.word      /* Group 0 time measurement register 4 */
754
#define     g0tm4l       g0tm4_addr.byte.low
755
#define     g0tm4h       g0tm4_addr.byte.high
756
757
#define     g0tm5        g0tm5_addr.word      /* Group 0 time measurement register 5 */
758
#define     g0tm5l       g0tm5_addr.byte.low
759
#define     g0tm5h       g0tm5_addr.byte.high
760
761
#define     g0tm6        g0tm6_addr.word      /* Group 0 time measurement register 6 */
762
#define     g0tm6l       g0tm6_addr.byte.low
763
#define     g0tm6h       g0tm6_addr.byte.high
764
765
#define     g0tm7        g0tm7_addr.word      /* Group 0 time measurement register 7 */
766
#define     g0tm7l       g0tm7_addr.byte.low
767
#define     g0tm7h       g0tm7_addr.byte.high
768
769
#define     g1tm0        g1tm0_addr.word      /* Group 1 time measurement register 0 */
770
#define     g1tm0l       g1tm0_addr.byte.low
771
#define     g1tm0h       g1tm0_addr.byte.high
772
773
#define     g1tm1        g1tm1_addr.word      /* Group 1 time measurement register 1 */
774
#define     g1tm1l       g1tm1_addr.byte.low
775
#define     g1tm1h       g1tm1_addr.byte.high
776
777
#define     g1tm2        g1tm2_addr.word      /* Group 1 time measurement register 2 */
778
#define     g1tm2l       g1tm2_addr.byte.low
779
#define     g1tm2h       g1tm2_addr.byte.high
780
781
#define     g1tm3        g1tm3_addr.word      /* Group 1 time measurement register 3 */
782
#define     g1tm3l       g1tm3_addr.byte.low
783
#define     g1tm3h       g1tm3_addr.byte.high
784
785
#define     g1tm4        g1tm4_addr.word      /* Group 1 time measurement register 4 */
786
#define     g1tm4l       g1tm4_addr.byte.low
787
#define     g1tm4h       g1tm4_addr.byte.high
788
789
#define     g1tm5        g1tm5_addr.word      /* Group 1 time measurement register 5 */
790
#define     g1tm5l       g1tm5_addr.byte.low
791
#define     g1tm5h       g1tm5_addr.byte.high
792
793
#define     g1tm6        g1tm6_addr.word      /* Group 1 time measurement register 6 */
794
#define     g1tm6l       g1tm6_addr.byte.low
795
#define     g1tm6h       g1tm6_addr.byte.high
796
797
#define     g1tm7        g1tm7_addr.word      /* Group 1 time measurement register 7 */
798
#define     g1tm7l       g1tm7_addr.byte.low
799
#define     g1tm7h       g1tm7_addr.byte.high
800
801
#define     g0po0        g0po0_addr.word      /* Group 0 waveform generate register 0 */
802
#define     g0po0l       g0po0_addr.byte.low
803
#define     g0po0h       g0po0_addr.byte.high
804
805
#define     g0po1        g0po1_addr.word      /* Group 0 waveform generate register 1 */
806
#define     g0po1l       g0po1_addr.byte.low
807
#define     g0po1h       g0po1_addr.byte.high
808
809
#define     g0po2        g0po2_addr.word      /* Group 0 waveform generate register 2 */
810
#define     g0po2l       g0po2_addr.byte.low
811
#define     g0po2h       g0po2_addr.byte.high
812
813
#define     g0po3        g0po3_addr.word      /* Group 0 waveform generate register 3 */
814
#define     g0po3l       g0po3_addr.byte.low
815
#define     g0po3h       g0po3_addr.byte.high
816
817
#define     g0po4        g0po4_addr.word      /* Group 0 waveform generate register 4 */
818
#define     g0po4l       g0po4_addr.byte.low
819
#define     g0po4h       g0po4_addr.byte.high
820
821
#define     g0po5        g0po5_addr.word      /* Group 0 waveform generate register 5 */
822
#define     g0po5l       g0po5_addr.byte.low
823
#define     g0po5h       g0po5_addr.byte.high
824
825
#define     g0po6        g0po6_addr.word      /* Group 0 waveform generate register 6 */
826
#define     g0po6l       g0po6_addr.byte.low
827
#define     g0po6h       g0po6_addr.byte.high
828
829
#define     g0po7        g0po7_addr.word      /* Group 0 waveform generate register 7 */
830
#define     g0po7l       g0po7_addr.byte.low
831
#define     g0po7h       g0po7_addr.byte.high
832
833
#define     g1po0        g1po0_addr.word      /* Group 1 waveform generate register 0 */
834
#define     g1po0l       g1po0_addr.byte.low
835
#define     g1po0h       g1po0_addr.byte.high
836
837
#define     g1po1        g1po1_addr.word      /* Group 1 waveform generate register 1 */
838
#define     g1po1l       g1po1_addr.byte.low
839
#define     g1po1h       g1po1_addr.byte.high
840
841
#define     g1po2        g1po2_addr.word      /* Group 1 waveform generate register 2 */
842
#define     g1po2l       g1po2_addr.byte.low
843
#define     g1po2h       g1po2_addr.byte.high
844
845
#define     g1po3        g1po3_addr.word      /* Group 1 waveform generate register 3 */
846
#define     g1po3l       g1po3_addr.byte.low
847
#define     g1po3h       g1po3_addr.byte.high
848
849
#define     g1po4        g1po4_addr.word      /* Group 1 waveform generate register 4 */
850
#define     g1po4l       g1po4_addr.byte.low
851
#define     g1po4h       g1po4_addr.byte.high
852
853
#define     g1po5        g1po5_addr.word      /* Group 1 waveform generate register 5 */
854
#define     g1po5l       g1po5_addr.byte.low
855
#define     g1po5h       g1po5_addr.byte.high
856
857
#define     g1po6        g1po6_addr.word      /* Group 1 waveform generate register 6 */
858
#define     g1po6l       g1po6_addr.byte.low
859
#define     g1po6h       g1po6_addr.byte.high
860
861
#define     g1po7        g1po7_addr.word      /* Group 1 waveform generate register 7 */
862
#define     g1po7l       g1po7_addr.byte.low
863
#define     g1po7h       g1po7_addr.byte.high
864
865
866
/*------------------------------------------------------
867
    SI/O receive buffer register
868
------------------------------------------------------*/
869
union{
870
    struct{
871
        char    b0:1;
872
        char    b1:1;
873
        char    b2:1;
874
        char    b3:1;
875
        char    b4:1;
876
        char    b5:1;
877
        char    b6:1;
878
        char    b7:1;
879
        char    b8:1;
880
        char    b9:1;
881
        char    b10:1;
882
        char    b11:1;
883
        char    oer:1;              /* Overrun error flag */
884
        char    fer:1;              /* Framing error flag */
885
        char    per:1;              /* Parity error flag */
886
        char    sum:1;              /* Error sum flag */
887
    }bit;
888
    struct{
889
        char    low;                /* Low  8 bit */
890
        char    high;               /* High 8 bit */
891
    }byte;
892
    unsigned short  word;
893
}g0rb_addr,g1rb_addr;
894
895
/*------------------------------------------------------
896
     g0rb
897
------------------------------------------------------*/
898
#define     g0rb        g0rb_addr.word
899
#define     g0rbl       g0rb_addr.byte.low
900
#define     g0rbh       g0rb_addr.byte.high
901
902
#define     oer_g0rb    g0rb_addr.bit.oer   /* Overrun error flag */
903
#define     fer_g0rb    g0rb_addr.bit.fer   /* Framing error flag */
904
//#define     per_g0rb    g0rb_addr.bit.per   /* Parity error flag */
905
//#define     sum_g0rb    g0rb_addr.bit.sum   /* Error sum flag */
906
907
/*------------------------------------------------------
908
     g1rb
909
------------------------------------------------------*/
910
#define     g1rb        g1rb_addr.word
911
#define     g1rbl       g1rb_addr.byte.low
912
#define     g1rbh       g1rb_addr.byte.high
913
914
#define     oer_g1rb    g1rb_addr.bit.oer   /* Overrun error flag */
915
#define     fer_g1rb    g1rb_addr.bit.fer   /* Framing error flag */
916
//#define     per_g1rb    g1rb_addr.bit.per   /* Parity error flag */
917
//#define     sum_g1rb    g1rb_addr.bit.sum   /* Error sum flag */
918
919
920
#define     g0tcrc        g0tcrc_addr.word      /* Group 0 transmit CRC code register */
921
#define     g0tcrcl       g0tcrc_addr.byte.low
922
#define     g0tcrch       g0tcrc_addr.byte.high
923
924
#define     g1tcrc        g1tcrc_addr.word      /* Group 1 transmit CRC code register */
925
#define     g1tcrcl       g1tcrc_addr.byte.low
926
#define     g1tcrch       g1tcrc_addr.byte.high
927
928
929
#define     g0rcrc        g0rcrc_addr.word      /* Group 0 receive CRC code register */
930
#define     g0rcrcl       g0rcrc_addr.byte.low
931
#define     g0rcrch       g0rcrc_addr.byte.high
932
933
#define     g1rcrc        g1rcrc_addr.word       /* Group 1 receive CRC code register */
934
#define     g1rcrcl       g1rcrc_addr.byte.low
935
#define     g1rcrch       g1rcrc_addr.byte.high
936
937
/********************************************************
938
*   group 2                                             *
939
********************************************************/
940
941
#define     g2bt        g2bt_addr.word      /* Group 2 base timer register */
942
#define     g2btl       g2bt_addr.byte.low
943
#define     g2bth       g2bt_addr.byte.high
944
945
#define     g2po0        g2po0_addr.word      /* Group 2 waveform generate register 0 */
946
#define     g2po0l       g2po0_addr.byte.low
947
#define     g2po0h       g2po0_addr.byte.high
948
949
#define     g2po1        g2po1_addr.word      /* Group 2 waveform generate register 1 */
950
#define     g2po1l       g2po1_addr.byte.low
951
#define     g2po1h       g2po1_addr.byte.high
952
953
#define     g2po2        g2po2_addr.word      /* Group 2 waveform generate register 2 */
954
#define     g2po2l       g2po2_addr.byte.low
955
#define     g2po2h       g2po2_addr.byte.high
956
957
#define     g2po3        g2po3_addr.word      /* Group 2 waveform generate register 3 */
958
#define     g2po3l       g2po3_addr.byte.low
959
#define     g2po3h       g2po3_addr.byte.high
960
961
#define     g2po4        g2po4_addr.word      /* Group 2 waveform generate register 4 */
962
#define     g2po4l       g2po4_addr.byte.low
963
#define     g2po4h       g2po4_addr.byte.high
964
965
#define     g2po5        g2po5_addr.word      /* Group 2 waveform generate register 5 */
966
#define     g2po5l       g2po5_addr.byte.low
967
#define     g2po5h       g2po5_addr.byte.high
968
969
#define     g2po6        g2po6_addr.word      /* Group 2 waveform generate register 6 */
970
#define     g2po6l       g2po6_addr.byte.low
971
#define     g2po6h       g2po6_addr.byte.high
972
973
#define     g2po7        g2po7_addr.word      /* Group 2 waveform generate register 7 */
974
#define     g2po7l       g2po7_addr.byte.low
975
#define     g2po7h       g2po7_addr.byte.high
976
977
/*------------------------------------------------------
978
     Group 2 SI/O transmit buffer register
979
------------------------------------------------------*/
980
union{
981
    struct{
982
        char    b0:1;
983
        char    b1:1;
984
        char    b2:1;
985
        char    b3:1;
986
        char    b4:1;
987
        char    b5:1;
988
        char    b6:1;
989
        char    b7:1;
990
        char    sz0:1;
991
        char    sz1:1;
992
        char    sz2:1;
993
        char    b11:1;
994
        char    b12:1;
995
        char    a:1;
996
        char    pc:1;
997
        char    p:1;
998
    }bit;
999
    struct{
1000
        char    low;                /* Low  8 bit */
1001
        char    high;               /* High 8 bit */
1002
    }byte;
1003
    unsigned short  word;
1004
}g2tb_addr;
1005
1006
/*------------------------------------------------------
1007
     g2tb
1008
------------------------------------------------------*/
1009
#define     g2tb        g2tb_addr.word
1010
#define     g2tbl       g2tb_addr.byte.low
1011
#define     g2tbh       g2tb_addr.byte.high
1012
1013
#define     sz0_g2tb    g2tb_addr.bit.sz0
1014
#define     sz1_g2tb    g2tb_addr.bit.sz1
1015
#define     sz2_g2tb    g2tb_addr.bit.sz2
1016
#define     a_g2tb      g2tb_addr.bit.a
1017
#define     pc_g2tb     g2tb_addr.bit.pc
1018
#define     p_g2tb      g2tb_addr.bit.p
1019
1020
/*------------------------------------------------------
1021
    Group 2 SI/O receive buffer register
1022
------------------------------------------------------*/
1023
union{
1024
    struct{
1025
        char    b0:1;
1026
        char    b1:1;
1027
        char    b2:1;
1028
        char    b3:1;
1029
        char    b4:1;
1030
        char    b5:1;
1031
        char    b6:1;
1032
        char    b7:1;
1033
        char    b8:1;
1034
        char    b9:1;
1035
        char    b10:1;
1036
        char    b11:1;
1037
        char    oer:1;
1038
        char    b13:1;
1039
        char    b14:1;
1040
        char    b15:1;
1041
    }bit;
1042
    struct{
1043
        char    low;                /* Low  8 bit */
1044
        char    high;               /* High 8 bit */
1045
    }byte;
1046
    unsigned short  word;
1047
}g2rb_addr;
1048
1049
/*------------------------------------------------------
1050
     g2rb
1051
------------------------------------------------------*/
1052
#define     g2rb        g2rb_addr.word
1053
#define     g2rbl       g2rb_addr.byte.low
1054
#define     g2rbh       g2rb_addr.byte.high
1055
1056
#define     oer_g2rb    g2rb_addr.bit.oer
1057
1058
#define     iear        iear_addr.word                 /* Group 2 IEBus address register */
1059
#define     iearl       iear_addr.byte.low
1060
#define     iearh       iear_addr.byte.high
1061
1062
1063
/********************************************************
1064
*   group 3                                             *
1065
********************************************************/
1066
1067
#define     g3bt        g3bt_addr.word      /* Group 3 base timer register */
1068
#define     g3btl       g3bt_addr.byte.low
1069
#define     g3bth       g3bt_addr.byte.high
1070
1071
#define     g3po0        g3po0_addr.word      /* Group 3 waveform generate register 0 */
1072
#define     g3po0l       g3po0_addr.byte.low
1073
#define     g3po0h       g3po0_addr.byte.high
1074
1075
#define     g3po1        g3po1_addr.word      /* Group 3 waveform generate register 1 */
1076
#define     g3po1l       g3po1_addr.byte.low
1077
#define     g3po1h       g3po1_addr.byte.high
1078
1079
#define     g3po2        g3po2_addr.word      /* Group 3 waveform generate register 2 */
1080
#define     g3po2l       g3po2_addr.byte.low
1081
#define     g3po2h       g3po2_addr.byte.high
1082
1083
#define     g3po3        g3po3_addr.word      /* Group 3 waveform generate register 3 */
1084
#define     g3po3l       g3po3_addr.byte.low
1085
#define     g3po3h       g3po3_addr.byte.high
1086
1087
#define     g3po4        g3po4_addr.word      /* Group 3 waveform generate register 4 */
1088
#define     g3po4l       g3po4_addr.byte.low
1089
#define     g3po4h       g3po4_addr.byte.high
1090
1091
#define     g3po5        g3po5_addr.word      /* Group 3 waveform generate register 5 */
1092
#define     g3po5l       g3po5_addr.byte.low
1093
#define     g3po5h       g3po5_addr.byte.high
1094
1095
#define     g3po6        g3po6_addr.word      /* Group 3 waveform generate register 6 */
1096
#define     g3po6l       g3po6_addr.byte.low
1097
#define     g3po6h       g3po6_addr.byte.high
1098
1099
#define     g3po7        g3po7_addr.word      /* Group 3 waveform generate register 7 */
1100
#define     g3po7l       g3po7_addr.byte.low
1101
#define     g3po7h       g3po7_addr.byte.high
1102
1103
1104
#define     g3mk4        g3mk4_addr.word     /* Group 3 waveform generate mask register 4 */
1105
#define     g3mk4l       g3mk4_addr.byte.low
1106
#define     g3mk4h       g3mk4_addr.byte.high
1107
1108
#define     g3mk5        g3mk5_addr.word     /* Group 3 waveform generate mask register 5 */
1109
#define     g3mk5l       g3mk5_addr.byte.low
1110
#define     g3mk5h       g3mk5_addr.byte.high
1111
1112
#define     g3mk6        g3mk6_addr.word     /* Group 3 waveform generate mask register 6 */
1113
#define     g3mk6l       g3mk6_addr.byte.low
1114
#define     g3mk6h       g3mk6_addr.byte.high
1115
1116
#define     g3mk7        g3mk7_addr.word      /* Group 3 waveform generate mask register 7 */
1117
#define     g3mk7l       g3mk7_addr.byte.low
1118
#define     g3mk7h       g3mk7_addr.byte.high
1119
1120
1121
#define     g3tb        g3tb_addr.word      /* Group 3 SI/O transmit buffer register */
1122
#define     g3tbl       g3tb_addr.byte.low
1123
#define     g3tbh       g3tb_addr.byte.high
1124
1125
#define     g3rb        g3rb_addr.word      /* Group 3 SI/O receive buffer register */
1126
#define     g3rbl       g3rb_addr.byte.low
1127
#define     g3rbh       g3rb_addr.byte.high
1128
1129
#define     hcnt        hcnt_addr.word     /* Group 3 high-speed HDLC transmit counter */
1130
#define     hcntl       hcnt_addr.byte.low
1131
#define     hcnth       hcnt_addr.byte.high
1132
1133
#define     hadr0        hadr0_addr.word   /* Group 3 high-speed HDLC data compare register 0 */
1134
#define     hadr0l       hadr0_addr.byte.low
1135
#define     hadr0h       hadr0_addr.byte.high
1136
1137
#define     hadr1        hadr1_addr.word   /* Group 3 high-speed HDLC data compare register 1 */
1138
#define     hadr1l       hadr1_addr.byte.low
1139
#define     hadr1h       hadr1_addr.byte.high
1140
1141
#define     hadr2        hadr2_addr.word   /* Group 3 high-speed HDLC data compare register 2 */
1142
#define     hadr2l       hadr2_addr.byte.low
1143
#define     hadr2h       hadr2_addr.byte.high
1144
1145
#define     hadr3        hadr3_addr.word   /* Group 3 high-speed HDLC data compare register 3 */
1146
#define     hadr3l       hadr3_addr.byte.low
1147
#define     hadr3h       hadr3_addr.byte.high
1148
1149
#define     hmsk0        hmsk0_addr.word   /* Group 3 high-speed HDLC data mask register 0 */
1150
#define     hmsk0l       hmsk0_addr.byte.low
1151
#define     hmsk0h       hmsk0_addr.byte.high
1152
1153
#define     hmsk1        hmsk1_addr.word   /* Group 3 high-speed HDLC data mask register 1 */
1154
#define     hmsk1l       hmsk1_addr.byte.low
1155
#define     hmsk1h       hmsk1_addr.byte.high
1156
1157
#define     hmsk2        hmsk2_addr.word   /* Group 3 high-speed HDLC data mask register 2 */
1158
#define     hmsk2l       hmsk2_addr.byte.low
1159
#define     hmsk2h       hmsk2_addr.byte.high
1160
1161
#define     hmsk3        hmsk3_addr.word   /* Group 3 high-speed HDLC data mask register 3 */
1162
#define     hmsk3l       hmsk3_addr.byte.low
1163
#define     hmsk3h       hmsk3_addr.byte.high
1164
1165
1166
/********************************************************
1167
*   declare SFR bit                                     *
1168
********************************************************/
1169
struct bit_def {
1170
        char    b0:1;
1171
        char    b1:1;
1172
        char    b2:1;
1173
        char    b3:1;
1174
        char    b4:1;
1175
        char    b5:1;
1176
        char    b6:1;
1177
        char    b7:1;
1178
};
1179
union byte_def{
1180
    struct bit_def bit;
1181
    char    byte;
1182
};
1183
1184
/*------------------------------------------------------
1185
    DRAM control register
1186
------------------------------------------------------*/
1187
union byte_def dramcont_addr;
1188
#define     dramcont        dramcont_addr.byte
1189
1190
#define     wt_dramcont      dramcont_addr.bit.b0
1191
#define     ar0_dramcont     dramcont_addr.bit.b1
1192
#define     ar1_dramcont     dramcont_addr.bit.b2
1193
#define     ar2_dramcont     dramcont_addr.bit.b3
1194
#define     sref_dramcont    dramcont_addr.bit.b7
1195
1196
/*------------------------------------------------------
1197
    DRAM refresh interval set register
1198
------------------------------------------------------*/
1199
union byte_def refcnt_addr;
1200
#define     refcnt      refcnt_addr.byte
1201
1202
//#define     refcnt0     refcnt_addr.bit.b0
1203
//#define     refcnt1     refcnt_addr.bit.b1
1204
//#define     refcnt2     refcnt_addr.bit.b2
1205
//#define     refcnt3     refcnt_addr.bit.b3
1206
//#define     refcnt4     refcnt_addr.bit.b4
1207
//#define     refcnt5     refcnt_addr.bit.b5
1208
//#define     refcnt6     refcnt_addr.bit.b6
1209
//#define     refcnt7     refcnt_addr.bit.b7
1210
1211
/*------------------------------------------------------
1212
    Flash Memory Control Register 2
1213
------------------------------------------------------*/
1214
union byte_def fmr2_addr;
1215
#define     fmr2      fmr2_addr.byte
1216
1217
#define     fmr20     fmr2_addr.bit.b0
1218
#define     fmr22     fmr2_addr.bit.b2
1219
1220
/*------------------------------------------------------
1221
    Flash Memory Control Register 1
1222
------------------------------------------------------*/
1223
union byte_def fmr1_addr;
1224
#define     fmr1      fmr1_addr.byte
1225
1226
#define     fmr10     fmr1_addr.bit.b0
1227
#define     fmr11     fmr1_addr.bit.b1
1228
#define     fmr14     fmr1_addr.bit.b4
1229
#define     fmr15     fmr1_addr.bit.b5
1230
1231
/*------------------------------------------------------
1232
    Flash Memory Control Register 0
1233
------------------------------------------------------*/
1234
union byte_def fmr0_addr;
1235
#define     fmr0      fmr0_addr.byte
1236
1237
#define     fmr00     fmr0_addr.bit.b0
1238
#define     fmr01     fmr0_addr.bit.b1
1239
#define     fmr02     fmr0_addr.bit.b2
1240
#define     fmr03     fmr0_addr.bit.b3
1241
//#define     fmr04     fmr0_addr.bit.b4
1242
//#define     fmr05     fmr0_addr.bit.b5
1243
#define     fmr06     fmr0_addr.bit.b6
1244
//#define     fmr07     fmr0_addr.bit.b7
1245
1246
/*------------------------------------------------------
1247
    Processor mode register 0
1248
------------------------------------------------------*/
1249
union byte_def pm0_addr;
1250
#define     pm0     pm0_addr.byte
1251
1252
#define     pm00        pm0_addr.bit.b0     /* Processor mode bit */
1253
#define     pm01        pm0_addr.bit.b1     /* Processor mode bit */
1254
#define     pm02        pm0_addr.bit.b2     /* R/W mode select bit */
1255
#define     pm03        pm0_addr.bit.b3     /* Software reset bit */
1256
#define     pm04        pm0_addr.bit.b4     /* Multiplexed bus space select bit */
1257
#define     pm05        pm0_addr.bit.b5     /* Multiplexed bus space select bit */
1258
//#define     pm06        pm0_addr.bit.b6     /* Reserved bit */
1259
#define     pm07        pm0_addr.bit.b7     /* BCLK output function select bit */
1260
1261
/*------------------------------------------------------
1262
    Processor mode register 1
1263
------------------------------------------------------*/
1264
union byte_def pm1_addr;
1265
#define     pm1     pm1_addr.byte
1266
1267
#define     pm10        pm1_addr.bit.b0     /* External memory area mode bit */
1268
#define     pm11        pm1_addr.bit.b1     /* External memory area mode bit */
1269
#define     pm12        pm1_addr.bit.b2     /* Internal memory wait bit */
1270
#define     pm13        pm1_addr.bit.b3     /* SFR wait bit */
1271
#define     pm14        pm1_addr.bit.b4     /* ALE pin select bit */
1272
#define     pm15        pm1_addr.bit.b5     /* ALE pin select bit */
1273
#define                pm17                pm1_addr.bit.b7                /* Reserved bit */
1274
1275
/*------------------------------------------------------
1276
    System clock control register 0
1277
------------------------------------------------------*/
1278
union byte_def cm0_addr;
1279
#define     cm0     cm0_addr.byte
1280
1281
#define     cm00        cm0_addr.bit.b0     /* Clock output function select bit */
1282
#define     cm01        cm0_addr.bit.b1     /* Clock output function select bit */
1283
#define     cm02        cm0_addr.bit.b2     /* WAIT peripheral function clock stop bit */
1284
#define     cm04        cm0_addr.bit.b4     /* Port Xc select bit */
1285
#define     cm05        cm0_addr.bit.b5     /* Main clock stop bit */
1286
#define     cm06        cm0_addr.bit.b6     /* WDT function select bit */
1287
#define     cm07        cm0_addr.bit.b7     /* System clock select bit (Xin-Xout or Xcin-Xcout)*/
1288
1289
/*------------------------------------------------------
1290
    System clock control register 1
1291
------------------------------------------------------*/
1292
union byte_def cm1_addr;
1293
#define     cm1     cm1_addr.byte
1294
1295
#define     cm10        cm1_addr.bit.b0     /* All clock stop control bit */
1296
//#define     cm15        cm1_addr.bit.b5     /* Xin-Xout drive capacity select bit */
1297
#define                cm17                cm1_addr.bit.b7                /* System clock select bit (Xin-Xout or PLL clock) */
1298
1299
/*------------------------------------------------------
1300
    Oscillation stop detect register
1301
------------------------------------------------------*/
1302
union byte_def cm2_addr;
1303
#define     cm2     cm2_addr.byte
1304
1305
#define     cm20        cm2_addr.bit.b0
1306
#define     cm21        cm2_addr.bit.b1
1307
#define     cm22        cm2_addr.bit.b2
1308
#define     cm23        cm2_addr.bit.b3
1309
#define     cm24        cm2_addr.bit.b4
1310
#define     cm25        cm2_addr.bit.b5
1311
#define     cm26        cm2_addr.bit.b6
1312
#define     cm27        cm2_addr.bit.b7
1313
1314
/*------------------------------------------------------
1315
    Wait control register
1316
------------------------------------------------------*/
1317
union byte_def wcr_addr;
1318
#define     wcr     wcr_addr.byte
1319
1320
#define     wcr0        wcr_addr.bit.b0
1321
#define     wcr1        wcr_addr.bit.b1
1322
#define     wcr2        wcr_addr.bit.b2
1323
#define     wcr3        wcr_addr.bit.b3
1324
#define     wcr4        wcr_addr.bit.b4
1325
#define     wcr5        wcr_addr.bit.b5
1326
#define     wcr6        wcr_addr.bit.b6
1327
#define     wcr7        wcr_addr.bit.b7
1328
1329
/*------------------------------------------------------
1330
    Address match interrupt enable register
1331
------------------------------------------------------*/
1332
union byte_def aier_addr;
1333
#define     aier        aier_addr.byte
1334
1335
#define     aier0       aier_addr.bit.b0    /* Address match interrupt 0 enable bit */
1336
#define     aier1       aier_addr.bit.b1    /* Address match interrupt 1 enable bit */
1337
#define     aier2       aier_addr.bit.b2    /* Address match interrupt 2 enable bit */  /*99.08.30*/
1338
#define     aier3       aier_addr.bit.b3    /* Address match interrupt 3 enable bit */  /*99.08.30*/
1339
1340
/*------------------------------------------------------
1341
    X-Y control register
1342
------------------------------------------------------*/
1343
union byte_def xyc_addr;
1344
#define     xyc     xyc_addr.byte
1345
1346
#define     xyc0        xyc_addr.bit.b0
1347
#define     xyc1        xyc_addr.bit.b1
1348
1349
/*------------------------------------------------------
1350
    Protect register
1351
------------------------------------------------------*/
1352
union byte_def prcr_addr;
1353
#define     prcr        prcr_addr.byte
1354
1355
#define     prc0        prcr_addr.bit.b0    /* Enables writing to system clock control register 0 and 1 */
1356
#define     prc1        prcr_addr.bit.b1    /* Enables writing to processor mode register 0 and 1 */
1357
#define     prc2        prcr_addr.bit.b2    /* Enables writing to port P9 direction register and function select register A3 */
1358
#define                prc3                prcr_addr.bit.b3        /* Enables writing VDC control register and PLL VDC control register */
1359
1360
/*------------------------------------------------------
1361
    External data bus width control register
1362
------------------------------------------------------*/
1363
union byte_def ds_addr;
1364
#define     ds      ds_addr.byte
1365
1366
#define     ds0     ds_addr.bit.b0
1367
#define     ds1     ds_addr.bit.b1
1368
#define     ds2     ds_addr.bit.b2
1369
#define     ds3     ds_addr.bit.b3
1370
1371
/*------------------------------------------------------
1372
    Main clock division register
1373
------------------------------------------------------*/
1374
union byte_def mcd_addr;
1375
#define     mcd     mcd_addr.byte
1376
1377
#define     mcd0        mcd_addr.bit.b0
1378
#define     mcd1        mcd_addr.bit.b1
1379
#define     mcd2        mcd_addr.bit.b2
1380
#define     mcd3        mcd_addr.bit.b3
1381
#define     mcd4        mcd_addr.bit.b4
1382
1383
/*------------------------------------------------------
1384
    PLL control register 0
1385
------------------------------------------------------*/
1386
union byte_def plc0_addr;
1387
#define     plc0     plc0_addr.byte
1388
1389
#define     plc00        plc0_addr.bit.b0
1390
#define     plc01        plc0_addr.bit.b1
1391
#define     plc02        plc0_addr.bit.b2
1392
//#define     plc03        plc0_addr.bit.b3
1393
#define     plc04        plc0_addr.bit.b4
1394
#define     plc05        plc0_addr.bit.b5
1395
#define     plc07        plc0_addr.bit.b7
1396
1397
/*------------------------------------------------------
1398
    PLL control register 1
1399
------------------------------------------------------*/
1400
union byte_def plc1_addr;
1401
#define     plc1     plc1_addr.byte
1402
1403
//#define     plc10        plc1_addr.bit.b0
1404
#define     plc11        plc1_addr.bit.b1
1405
//#define     plc12        plc1_addr.bit.b2
1406
1407
/*------------------------------------------------------
1408
   Count source prescaler register
1409
------------------------------------------------------*/
1410
union byte_def tcspr_addr;
1411
#define     tcspr     tcspr_addr.byte
1412
1413
#define     cnt0        tcspr_addr.bit.b0
1414
#define     cnt1        tcspr_addr.bit.b1
1415
#define     cnt2        tcspr_addr.bit.b2
1416
#define     cnt3        tcspr_addr.bit.b3
1417
#define     cst         tcspr_addr.bit.b7
1418
1419
/*------------------------------------------------------
1420
    Exit priority register
1421
------------------------------------------------------*/
1422
union byte_def rlvl_addr;
1423
#define     rlvl        rlvl_addr.byte
1424
1425
#define     rlvl0       rlvl_addr.bit.b0
1426
#define     rlvl1       rlvl_addr.bit.b1
1427
#define     rlvl2       rlvl_addr.bit.b2
1428
#define     fsit        rlvl_addr.bit.b3
1429
#define                dmaii                rlvl_addr.bit.b5
1430
1431
/*------------------------------------------------------
1432
    Interrupt cause select register
1433
------------------------------------------------------*/
1434
union byte_def ifsr_addr;
1435
#define     ifsr        ifsr_addr.byte
1436
1437
#define     ifsr0       ifsr_addr.bit.b0
1438
#define     ifsr1       ifsr_addr.bit.b1
1439
#define     ifsr2       ifsr_addr.bit.b2
1440
#define     ifsr3       ifsr_addr.bit.b3
1441
#define     ifsr4       ifsr_addr.bit.b4
1442
#define     ifsr5       ifsr_addr.bit.b5
1443
#define     ifsr6       ifsr_addr.bit.b6
1444
#define     ifsr7       ifsr_addr.bit.b7
1445
1446
/*------------------------------------------------------
1447
    Timer B2 special mode register
1448
------------------------------------------------------*/
1449
union byte_def tb2sc_addr;
1450
#define     tb2sc     tb2sc_addr.byte
1451
1452
#define     pwcon     tb2sc_addr.bit.b0
1453
1454
/*------------------------------------------------------
1455
    Watchdog timer start register
1456
------------------------------------------------------*/
1457
union byte_def wdts_addr;
1458
#define     wdts        wdts_addr.byte
1459
1460
/*------------------------------------------------------
1461
    CRC input register
1462
------------------------------------------------------*/
1463
union byte_def crcin_addr;
1464
#define     crcin       crcin_addr.byte
1465
1466
/*------------------------------------------------------
1467
    Watchdog timer control register
1468
------------------------------------------------------*/
1469
union byte_def wdc_addr;
1470
#define     wdc     wdc_addr.byte
1471
1472
//#define                wdc5                wdc_addr.bit.b5
1473
//#define                wdc6                wdc_addr.bit.b6
1474
#define     wdc7        wdc_addr.bit.b7     /* Prescaler select bit */
1475
1476
/*------------------------------------------------------
1477
    PLL VDC control register
1478
------------------------------------------------------*/
1479
union byte_def plv_addr;
1480
#define     plv     plv_addr.byte
1481
1482
#define                plv00                plv_addr.bit.b0
1483
//#define                plv01                plv_addr.bit.b1
1484
1485
/*------------------------------------------------------
1486
    Count start flag
1487
------------------------------------------------------*/
1488
union byte_def tabsr_addr;
1489
#define     tabsr       tabsr_addr.byte
1490
1491
#define     ta0s        tabsr_addr.bit.b0   /* Timer A0 count start flag */
1492
#define     ta1s        tabsr_addr.bit.b1   /* Timer A1 count start flag */
1493
#define     ta2s        tabsr_addr.bit.b2   /* Timer A2 count start flag */
1494
#define     ta3s        tabsr_addr.bit.b3   /* Timer A3 count start flag */
1495
#define     ta4s        tabsr_addr.bit.b4   /* Timer A4 count start flag */
1496
#define     tb0s        tabsr_addr.bit.b5   /* Timer B0 count start flag */
1497
#define     tb1s        tabsr_addr.bit.b6   /* Timer B1 count start flag */
1498
#define     tb2s        tabsr_addr.bit.b7   /* Timer B2 count start flag */
1499
1500
/*------------------------------------------------------
1501
    Timer B3,4,5 count start flag
1502
------------------------------------------------------*/
1503
union byte_def tbsr_addr;
1504
#define     tbsr        tbsr_addr.byte
1505
1506
#define     tb3s        tbsr_addr.bit.b5    /* Timer B3 count start flag */
1507
#define     tb4s        tbsr_addr.bit.b6    /* Timer B4 count start flag */
1508
#define     tb5s        tbsr_addr.bit.b7    /* Timer B5 count start flag */
1509
1510
/*------------------------------------------------------
1511
    Three-phase PWM control regester 0
1512
------------------------------------------------------*/
1513
union byte_def invc0_addr;
1514
#define     invc0       invc0_addr.byte
1515
1516
#define     inv00       invc0_addr.bit.b0
1517
#define     inv01       invc0_addr.bit.b1
1518
#define     inv02       invc0_addr.bit.b2
1519
#define     inv03       invc0_addr.bit.b3
1520
#define     inv04       invc0_addr.bit.b4
1521
#define     inv05       invc0_addr.bit.b5
1522
#define     inv06       invc0_addr.bit.b6
1523
#define     inv07       invc0_addr.bit.b7
1524
1525
/*------------------------------------------------------
1526
    Three-phase PWM control regester 1
1527
------------------------------------------------------*/
1528
union byte_def invc1_addr;
1529
#define     invc1       invc1_addr.byte
1530
1531
#define     inv10       invc1_addr.bit.b0
1532
#define     inv11       invc1_addr.bit.b1
1533
#define     inv12       invc1_addr.bit.b2
1534
#define     inv13       invc1_addr.bit.b3
1535
#define     inv14       invc1_addr.bit.b4
1536
#define     inv15       invc1_addr.bit.b5
1537
//#define     inv16       invc1_addr.bit.b6
1538
#define     inv17       invc1_addr.bit.b7
1539
1540
/*------------------------------------------------------
1541
    Three-phase output buffer register 0
1542
------------------------------------------------------*/
1543
union byte_def idb0_addr;
1544
#define     idb0        idb0_addr.byte
1545
1546
#define     du0         idb0_addr.bit.b0
1547
#define     dub0        idb0_addr.bit.b1
1548
#define     dv0         idb0_addr.bit.b2
1549
#define     dvb0        idb0_addr.bit.b3
1550
#define     dw0         idb0_addr.bit.b4
1551
#define     dwb0        idb0_addr.bit.b5
1552
1553
/*------------------------------------------------------
1554
    Three-phase output buffer register 1
1555
------------------------------------------------------*/
1556
union byte_def idb1_addr;
1557
#define     idb1        idb1_addr.byte
1558
1559
#define     du1         idb1_addr.bit.b0
1560
#define     dub1        idb1_addr.bit.b1
1561
#define     dv1         idb1_addr.bit.b2
1562
#define     dvb1        idb1_addr.bit.b3
1563
#define     dw1         idb1_addr.bit.b4
1564
#define     dwb1        idb1_addr.bit.b5
1565
1566
/*------------------------------------------------------
1567
     Dead time timer ; Use "MOV" instruction when writing to this register.
1568
------------------------------------------------------*/
1569
union byte_def dtt_addr;
1570
#define     dtt     dtt_addr.byte
1571
1572
/*------------------------------------------------------
1573
    Timer B2 interrupt occurrences frequency set counter ; Use "MOV" instruction when writing to this register.
1574
------------------------------------------------------*/
1575
union byte_def ictb2_addr;
1576
#define     ictb2       ictb2_addr.byte
1577
1578
/*------------------------------------------------------
1579
    One-shot start flag
1580
------------------------------------------------------*/
1581
union byte_def onsf_addr;
1582
#define     onsf        onsf_addr.byte
1583
1584
#define     ta0os       onsf_addr.bit.b0    /* Timer A0 one-shot start flag */
1585
#define     ta1os       onsf_addr.bit.b1    /* Timer A1 one-shot start flag */
1586
#define     ta2os       onsf_addr.bit.b2    /* Timer A2 one-shot start flag */
1587
#define     ta3os       onsf_addr.bit.b3    /* Timer A3 one-shot start flag */
1588
#define     ta4os       onsf_addr.bit.b4    /* Timer A4 one-shot start flag */
1589
#define     tazie       onsf_addr.bit.b5    /* Timer A4 Z-phase input valid bit */
1590
#define     ta0tgl      onsf_addr.bit.b6    /* Timer A0 event/trigger select bit */
1591
#define     ta0tgh      onsf_addr.bit.b7    /* Timer A0 event/trigger select bit */
1592
1593
/*------------------------------------------------------
1594
    Clock prescaler reset flag
1595
------------------------------------------------------*/
1596
union byte_def cpsrf_addr;
1597
#define     cpsrf       cpsrf_addr.byte
1598
1599
#define     cpsr        cpsrf_addr.bit.b7   /* Clock prescaler reset flag */
1600
1601
/*------------------------------------------------------
1602
    Trigger select register
1603
------------------------------------------------------*/
1604
union byte_def trgsr_addr;
1605
#define     trgsr       trgsr_addr.byte
1606
1607
#define     ta1tgl      trgsr_addr.bit.b0   /* Timer A1 event/trigger select bit */
1608
#define     ta1tgh      trgsr_addr.bit.b1   /* Timer A1 event/trigger select bit */
1609
#define     ta2tgl      trgsr_addr.bit.b2   /* Timer A2 event/trigger select bit */
1610
#define     ta2tgh      trgsr_addr.bit.b3   /* Timer A2 event/trigger select bit */
1611
#define     ta3tgl      trgsr_addr.bit.b4   /* Timer A3 event/trigger select bit */
1612
#define     ta3tgh      trgsr_addr.bit.b5   /* Timer A3 event/trigger select bit */
1613
#define     ta4tgl      trgsr_addr.bit.b6   /* Timer A4 event/trigger select bit */
1614
#define     ta4tgh      trgsr_addr.bit.b7   /* Timer A4 event/trigger select bit */
1615
1616
/*------------------------------------------------------
1617
    Up Down Flag
1618
------------------------------------------------------*/
1619
union byte_def   udf_addr;               /* Up/down flag */
1620
#define     udf     udf_addr.byte
1621
1622
#define                ta0ud        udf_addr.bit.b0
1623
#define                ta1ud        udf_addr.bit.b1
1624
#define                ta2ud        udf_addr.bit.b2
1625
#define                ta3ud        udf_addr.bit.b3
1626
#define                ta4ud        udf_addr.bit.b4
1627
#define                ta2p        udf_addr.bit.b5
1628
#define                ta3p        udf_addr.bit.b6
1629
#define                ta4p        udf_addr.bit.b7
1630
1631
/*------------------------------------------------------
1632
    UART0 transmit/receive control register 1
1633
------------------------------------------------------*/
1634
union byte_def u0c1_addr;
1635
#define     u0c1        u0c1_addr.byte
1636
#define     te_u0c1     u0c1_addr.bit.b0    /* Transmit enable bit */
1637
#define     ti_u0c1     u0c1_addr.bit.b1    /* Transmit buffer empty flag */
1638
#define     re_u0c1     u0c1_addr.bit.b2    /* Receive enable bit */
1639
#define     ri_u0c1     u0c1_addr.bit.b3    /* Receive complete flag */
1640
#define     u0irs_u0c1       u0c1_addr.bit.b4    /* UART2 transmit interrupt cause select bit */
1641
#define     u0rrm_u0c1       u0c1_addr.bit.b5    /* UART2 continuous receive mode enable bit */
1642
#define     u0lch_u0c1       u0c1_addr.bit.b6    /* Data logic select bit */
1643
#define     sclkstpb_u0c1 u0c1_addr.bit.b7   /* Clock divide synchronizing stop bit */
1644
#define     u0ere_u0c1       u0c1_addr.bit.b7    /* Error signal output enable bit */
1645
1646
/*------------------------------------------------------
1647
    UART1 transmit/receive control register 1
1648
------------------------------------------------------*/
1649
union byte_def u1c1_addr;
1650
#define     u1c1        u1c1_addr.byte
1651
#define     te_u1c1     u1c1_addr.bit.b0    /* Transmit enable bit */
1652
#define     ti_u1c1     u1c1_addr.bit.b1    /* Transmit buffer empty flag */
1653
#define     re_u1c1     u1c1_addr.bit.b2    /* Receive enable bit */
1654
#define     ri_u1c1     u1c1_addr.bit.b3    /* Receive complete flag */
1655
#define     u1irs_u1c1  u1c1_addr.bit.b4    /* UART2 transmit interrupt cause select bit */
1656
#define     u1rrm_u1c1  u1c1_addr.bit.b5    /* UART2 continuous receive mode enable bit */
1657
#define     u1lch_u1c1  u1c1_addr.bit.b6    /* Data logic select bit */
1658
#define     sclkstpb_u1c1 u1c1_addr.bit.b7    /* Clock divide synchronizing stop bit */
1659
#define     u1ere_u1c1    u1c1_addr.bit.b7    /* Error signal output enable bit */
1660
1661
/*------------------------------------------------------
1662
    UART2 transmit/receive control register 1
1663
------------------------------------------------------*/
1664
union byte_def u2c1_addr;
1665
#define     u2c1        u2c1_addr.byte
1666
#define     te_u2c1     u2c1_addr.bit.b0    /* Transmit enable bit */
1667
#define     ti_u2c1     u2c1_addr.bit.b1    /* Transmit buffer empty flag */
1668
#define     re_u2c1     u2c1_addr.bit.b2    /* Receive enable bit */
1669
#define     ri_u2c1     u2c1_addr.bit.b3    /* Receive complete flag */
1670
#define     u2irs_u2c1       u2c1_addr.bit.b4    /* UART2 transmit interrupt cause select bit */
1671
#define     u2rrm_u2c1       u2c1_addr.bit.b5    /* UART2 continuous receive mode enable bit */
1672
#define     u2lch_u2c1       u2c1_addr.bit.b6    /* Data logic select bit */
1673
#define     sclkstpb_u2c1 u2c1_addr.bit.b7   /* Clock divide synchronizing stop bit */
1674
#define     u2ere_u2c1       u2c1_addr.bit.b7    /* Error signal output enable bit */
1675
1676
/*------------------------------------------------------
1677
    UART3 transmit/receive control register 1
1678
------------------------------------------------------*/
1679
union byte_def u3c1_addr;
1680
#define     u3c1        u3c1_addr.byte
1681
#define     te_u3c1     u3c1_addr.bit.b0    /* Transmit enable bit */
1682
#define     ti_u3c1     u3c1_addr.bit.b1    /* Transmit buffer empty flag */
1683
#define     re_u3c1     u3c1_addr.bit.b2    /* Receive enable bit */
1684
#define     ri_u3c1     u3c1_addr.bit.b3    /* Receive complete flag */
1685
#define     u3irs_u3c1       u3c1_addr.bit.b4    /* UART3 transmit interrupt cause select bit */
1686
#define     u3rrm_u3c1       u3c1_addr.bit.b5    /* UART3 continuous receive mode enable bit */
1687
#define     u3lch_u3c1       u3c1_addr.bit.b6    /* Data logic select bit */
1688
#define     sclkstpb_u3c1 u3c1_addr.bit.b7   /* Clock divide synchronizing stop bit */
1689
#define     u3ere_u3c1       u3c1_addr.bit.b7    /* Error signal output enable bit */
1690
1691
/*------------------------------------------------------
1692
    UART4 transmit/receive control register 1
1693
------------------------------------------------------*/
1694
union byte_def u4c1_addr;
1695
#define     u4c1        u4c1_addr.byte
1696
#define     te_u4c1     u4c1_addr.bit.b0    /* Transmit enable bit */
1697
#define     ti_u4c1     u4c1_addr.bit.b1    /* Transmit buffer empty flag */
1698
#define     re_u4c1     u4c1_addr.bit.b2    /* Receive enable bit */
1699
#define     ri_u4c1     u4c1_addr.bit.b3    /* Receive complete flag */
1700
#define     u4irs_u4c1  u4c1_addr.bit.b4    /* UART4 transmit interrupt cause select bit */
1701
#define     u4rrm_u4c1  u4c1_addr.bit.b5    /* UART4 continuous receive mode enable bit */
1702
#define     u4lch_u4c1  u4c1_addr.bit.b6    /* Data logic select bit */
1703
#define     sclkstpb_u4c1 u4c1_addr.bit.b7    /* Clock divide synchronizing stop bit */
1704
#define     u4ere_u4c1   u4c1_addr.bit.b7    /* Error signal output enable bit */
1705
1706
/*------------------------------------------------------
1707
    A/D0 control register 0
1708
------------------------------------------------------*/
1709
union byte_def ad0con0_addr;
1710
#define     ad0con0      ad0con0_addr.byte
1711
1712
#define     ch0_ad0con0     ad0con0_addr.bit.b0  /* Analog input pin select bit */
1713
#define     ch1_ad0con0     ad0con0_addr.bit.b1  /* Analog input pin select bit */
1714
#define     ch2_ad0con0     ad0con0_addr.bit.b2  /* Analog input pin select bit */
1715
#define     md0_ad0con0     ad0con0_addr.bit.b3  /* A/D operation mode select bit 0 */
1716
#define     md1_ad0con0     ad0con0_addr.bit.b4  /* A/D operation mode select bit 0 */
1717
#define     trg_ad0con0     ad0con0_addr.bit.b5  /* Trigger select bit */
1718
#define     adst_ad0con0    ad0con0_addr.bit.b6  /* A/D conversion start flag */
1719
#define     cks0_ad0con0    ad0con0_addr.bit.b7  /* Frequency select bit 0 */
1720
1721
/*------------------------------------------------------
1722
    A/D0 control  register 1
1723
------------------------------------------------------*/
1724
union byte_def ad0con1_addr;
1725
#define     ad0con1      ad0con1_addr.byte
1726
1727
#define     scan0_ad0con1       ad0con1_addr.bit.b0  /* A/D sweep pin select bit */
1728
#define     scan1_ad0con1       ad0con1_addr.bit.b1  /* A/D sweep pin select bit */
1729
#define     md2_ad0con1         ad0con1_addr.bit.b2  /* A/D operation mode select bit 1 */
1730
#define     bits_ad0con1        ad0con1_addr.bit.b3  /* 8/10-bit mode select bit */
1731
#define     cks1_ad0con1        ad0con1_addr.bit.b4  /* Frequency select bit 1 */
1732
#define     vcut_ad0con1        ad0con1_addr.bit.b5  /* Vref connect bit */
1733
#define     opa0_ad0con1        ad0con1_addr.bit.b6  /* External op-amp connection mode bit */
1734
#define     opa1_ad0con1        ad0con1_addr.bit.b7  /* External op-amp connection mode bit */
1735
1736
/*------------------------------------------------------
1737
    A/D0 control register 2
1738
------------------------------------------------------*/
1739
union byte_def ad0con2_addr;
1740
#define     ad0con2      ad0con2_addr.byte
1741
1742
#define     smp_ad0con2         ad0con2_addr.bit.b0  /* A/D conversion method select bit */
1743
#define     ads_ad0con2         ad0con2_addr.bit.b4
1744
#define     trg0_ad0con2        ad0con2_addr.bit.b5
1745
#define     trg1_ad0con2        ad0con2_addr.bit.b6
1746
#define     pst_ad0con2         ad0con2_addr.bit.b7
1747
1748
/*------------------------------------------------------
1749
    A/D1 control register 0
1750
------------------------------------------------------*/
1751
union byte_def ad1con0_addr;
1752
#define     ad1con0      ad1con0_addr.byte
1753
1754
#define     ch0_ad1con0     ad1con0_addr.bit.b0  /* Analog input pin select bit */
1755
#define     ch1_ad1con0     ad1con0_addr.bit.b1  /* Analog input pin select bit */
1756
#define     ch2_ad1con0     ad1con0_addr.bit.b2  /* Analog input pin select bit */
1757
#define     md0_ad1con0     ad1con0_addr.bit.b3  /* A/D operation mode select bit 0 */
1758
#define     md1_ad1con0     ad1con0_addr.bit.b4  /* A/D operation mode select bit 0 */
1759
#define     trg_ad1con0     ad1con0_addr.bit.b5  /* Trigger select bit */
1760
#define     adst_ad1con0    ad1con0_addr.bit.b6  /* A/D conversion start flag */
1761
#define     cks0_ad1con0    ad1con0_addr.bit.b7  /* Frequency select bit 0 */
1762
1763
/*------------------------------------------------------
1764
    A/D1 control  register 1
1765
------------------------------------------------------*/
1766
union byte_def ad1con1_addr;
1767
#define     ad1con1      ad1con1_addr.byte
1768
1769
#define     scan0_ad1con1       ad1con1_addr.bit.b0  /* A/D sweep pin select bit */
1770
#define     scan1_ad1con1       ad1con1_addr.bit.b1  /* A/D sweep pin select bit */
1771
#define     md2_ad1con1         ad1con1_addr.bit.b2  /* A/D operation mode select bit 1 */
1772
#define     bits_ad1con1        ad1con1_addr.bit.b3  /* 8/10-bit mode select bit */
1773
#define     cks1_ad1con1        ad1con1_addr.bit.b4  /* Frequency select bit 1 */
1774
#define     vcut_ad1con1        ad1con1_addr.bit.b5  /* Vref connect bit */
1775
1776
/*------------------------------------------------------
1777
    A/D1 control register 2
1778
------------------------------------------------------*/
1779
union byte_def ad1con2_addr;
1780
#define     ad1con2      ad1con2_addr.byte
1781
1782
#define     smp_ad1con2         ad1con2_addr.bit.b0  /* A/D conversion method select bit */
1783
#define     aps0_ad1con2        ad1con2_addr.bit.b1
1784
#define     aps1_ad1con2        ad1con2_addr.bit.b2
1785
#define                trg0_ad1con2                ad1con2_addr.bit.b5
1786
#define                trg1_ad1con2                ad1con2_addr.bit.b6
1787
1788
/*------------------------------------------------------
1789
    D/A control register
1790
------------------------------------------------------*/
1791
union byte_def dacon_addr;
1792
#define     dacon       dacon_addr.byte
1793
1794
#define     da0e        dacon_addr.bit.b0   /* D/A0 output enable bit */
1795
#define     da1e        dacon_addr.bit.b1   /* D/A1 output enable bit */
1796
1797
/*------------------------------------------------------
1798
    Base timer start register
1799
------------------------------------------------------*/
1800
union byte_def btsr_addr;
1801
#define     btsr       btsr_addr.byte
1802
1803
#define     bt0s        btsr_addr.bit.b0
1804
#define     bt1s        btsr_addr.bit.b1
1805
#define     bt2s        btsr_addr.bit.b2
1806
#define     bt3s        btsr_addr.bit.b3
1807
1808
/*------------------------------------------------------
1809
    Group 0 base timer control register 0
1810
------------------------------------------------------*/
1811
union byte_def g0bcr0_addr;
1812
#define     g0bcr0       g0bcr0_addr.byte
1813
1814
#define     bck0_g0bcr0        g0bcr0_addr.bit.b0
1815
#define     bck1_g0bcr0        g0bcr0_addr.bit.b1
1816
#define     div0_g0bcr0        g0bcr0_addr.bit.b2
1817
#define     div1_g0bcr0        g0bcr0_addr.bit.b3
1818
#define     div2_g0bcr0        g0bcr0_addr.bit.b4
1819
#define     div3_g0bcr0        g0bcr0_addr.bit.b5
1820
#define     div4_g0bcr0        g0bcr0_addr.bit.b6
1821
#define     it_g0bcr0          g0bcr0_addr.bit.b7
1822
1823
/*------------------------------------------------------
1824
    Group 0 base timer control register 1
1825
------------------------------------------------------*/
1826
union byte_def g0bcr1_addr;
1827
#define     g0bcr1       g0bcr1_addr.byte
1828
1829
#define     rst0_g0bcr1        g0bcr1_addr.bit.b0
1830
#define     rst1_g0bcr1        g0bcr1_addr.bit.b1
1831
#define     rst2_g0bcr1        g0bcr1_addr.bit.b2
1832
#define                rst3_g0bcr1                   g0bcr1_addr.bit.b3
1833
#define     bts_g0bcr1         g0bcr1_addr.bit.b4
1834
#define     ud0_g0bcr1         g0bcr1_addr.bit.b5
1835
#define     ud1_g0bcr1         g0bcr1_addr.bit.b6
1836
#define     cas_g0bcr1         g0bcr1_addr.bit.b7
1837
1838
/*------------------------------------------------------
1839
    Group 0 time measurement control register 0
1840
------------------------------------------------------*/
1841
union byte_def g0tmcr0_addr;
1842
#define     g0tmcr0       g0tmcr0_addr.byte
1843
1844
#define     cts0_g0tmcr0      g0tmcr0_addr.bit.b0
1845
#define     cts1_g0tmcr0      g0tmcr0_addr.bit.b1
1846
#define     df0_g0tmcr0       g0tmcr0_addr.bit.b2
1847
#define     df1_g0tmcr0       g0tmcr0_addr.bit.b3
1848
#define     gt_g0tmcr0        g0tmcr0_addr.bit.b4
1849
#define     goc_g0tmcr0       g0tmcr0_addr.bit.b5
1850
#define     gsc_g0tmcr0       g0tmcr0_addr.bit.b6
1851
#define     pr_g0tmcr0        g0tmcr0_addr.bit.b7
1852
1853
/*------------------------------------------------------
1854
    Group 0 time measurement control register 1
1855
------------------------------------------------------*/
1856
union byte_def g0tmcr1_addr;
1857
#define     g0tmcr1       g0tmcr1_addr.byte
1858
1859
#define     cts0_g0tmcr1      g0tmcr1_addr.bit.b0
1860
#define     cts1_g0tmcr1      g0tmcr1_addr.bit.b1
1861
#define     df0_g0tmcr1       g0tmcr1_addr.bit.b2
1862
#define     df1_g0tmcr1       g0tmcr1_addr.bit.b3
1863
#define     gt_g0tmcr1        g0tmcr1_addr.bit.b4
1864
#define     goc_g0tmcr1       g0tmcr1_addr.bit.b5
1865
#define     gsc_g0tmcr1       g0tmcr1_addr.bit.b6
1866
#define     pr_g0tmcr1        g0tmcr1_addr.bit.b7
1867
1868
/*------------------------------------------------------
1869
    Group 0 time measurement control register 2
1870
------------------------------------------------------*/
1871
union byte_def g0tmcr2_addr;
1872
#define     g0tmcr2       g0tmcr2_addr.byte
1873
1874
#define     cts0_g0tmcr2      g0tmcr2_addr.bit.b0
1875
#define     cts1_g0tmcr2      g0tmcr2_addr.bit.b1
1876
#define     df0_g0tmcr2       g0tmcr2_addr.bit.b2
1877
#define     df1_g0tmcr2       g0tmcr2_addr.bit.b3
1878
#define     gt_g0tmcr2        g0tmcr2_addr.bit.b4
1879
#define     goc_g0tmcr2       g0tmcr2_addr.bit.b5
1880
#define     gsc_g0tmcr2       g0tmcr2_addr.bit.b6
1881
#define     pr_g0tmcr2        g0tmcr2_addr.bit.b7
1882
1883
/*------------------------------------------------------
1884
    Group 0 time measurement control register 3
1885
------------------------------------------------------*/
1886
union byte_def g0tmcr3_addr;
1887
#define     g0tmcr3       g0tmcr3_addr.byte
1888
1889
#define     cts0_g0tmcr3      g0tmcr3_addr.bit.b0
1890
#define     cts1_g0tmcr3      g0tmcr3_addr.bit.b1
1891
#define     df0_g0tmcr3       g0tmcr3_addr.bit.b2
1892
#define     df1_g0tmcr3       g0tmcr3_addr.bit.b3
1893
#define     gt_g0tmcr3        g0tmcr3_addr.bit.b4
1894
#define     goc_g0tmcr3       g0tmcr3_addr.bit.b5
1895
#define     gsc_g0tmcr3       g0tmcr3_addr.bit.b6
1896
#define     pr_g0tmcr3        g0tmcr3_addr.bit.b7
1897
1898
/*------------------------------------------------------
1899
    Group 0 time measurement control register 4
1900
------------------------------------------------------*/
1901
union byte_def g0tmcr4_addr;
1902
#define     g0tmcr4       g0tmcr4_addr.byte
1903
1904
#define     cts0_g0tmcr4      g0tmcr4_addr.bit.b0
1905
#define     cts1_g0tmcr4      g0tmcr4_addr.bit.b1
1906
#define     df0_g0tmcr4       g0tmcr4_addr.bit.b2
1907
#define     df1_g0tmcr4       g0tmcr4_addr.bit.b3
1908
#define     gt_g0tmcr4        g0tmcr4_addr.bit.b4
1909
#define     goc_g0tmcr4       g0tmcr4_addr.bit.b5
1910
#define     gsc_g0tmcr4       g0tmcr4_addr.bit.b6
1911
#define     pr_g0tmcr4        g0tmcr4_addr.bit.b7
1912
1913
/*------------------------------------------------------
1914
    Group 0 time measurement control register 5
1915
------------------------------------------------------*/
1916
union byte_def g0tmcr5_addr;
1917
#define     g0tmcr5       g0tmcr5_addr.byte
1918
1919
#define     cts0_g0tmcr5      g0tmcr5_addr.bit.b0
1920
#define     cts1_g0tmcr5      g0tmcr5_addr.bit.b1
1921
#define     df0_g0tmcr5       g0tmcr5_addr.bit.b2
1922
#define     df1_g0tmcr5       g0tmcr5_addr.bit.b3
1923
#define     gt_g0tmcr5        g0tmcr5_addr.bit.b4
1924
#define     goc_g0tmcr5       g0tmcr5_addr.bit.b5
1925
#define     gsc_g0tmcr5       g0tmcr5_addr.bit.b6
1926
#define     pr_g0tmcr5        g0tmcr5_addr.bit.b7
1927
1928
/*------------------------------------------------------
1929
    Group 0 time measurement control register 6
1930
------------------------------------------------------*/
1931
union byte_def g0tmcr6_addr;
1932
#define     g0tmcr6       g0tmcr6_addr.byte
1933
1934
#define     cts0_g0tmcr6      g0tmcr6_addr.bit.b0
1935
#define     cts1_g0tmcr6      g0tmcr6_addr.bit.b1
1936
#define     df0_g0tmcr6       g0tmcr6_addr.bit.b2
1937
#define     df1_g0tmcr6       g0tmcr6_addr.bit.b3
1938
#define     gt_g0tmcr6        g0tmcr6_addr.bit.b4
1939
#define     goc_g0tmcr6       g0tmcr6_addr.bit.b5
1940
#define     gsc_g0tmcr6       g0tmcr6_addr.bit.b6
1941
#define     pr_g0tmcr6        g0tmcr6_addr.bit.b7
1942
1943
/*------------------------------------------------------
1944
    Group 0 time measurement control register 7
1945
------------------------------------------------------*/
1946
union byte_def g0tmcr7_addr;
1947
#define     g0tmcr7       g0tmcr7_addr.byte
1948
1949
#define     cts0_g0tmcr7      g0tmcr7_addr.bit.b0
1950
#define     cts1_g0tmcr7      g0tmcr7_addr.bit.b1
1951
#define     df0_g0tmcr7       g0tmcr7_addr.bit.b2
1952
#define     df1_g0tmcr7       g0tmcr7_addr.bit.b3
1953
#define     gt_g0tmcr7        g0tmcr7_addr.bit.b4
1954
#define     goc_g0tmcr7       g0tmcr7_addr.bit.b5
1955
#define     gsc_g0tmcr7       g0tmcr7_addr.bit.b6
1956
#define     pr_g0tmcr7        g0tmcr7_addr.bit.b7
1957
1958
/*------------------------------------------------------
1959
    Group 0 time measurement prescaler register 6
1960
------------------------------------------------------*/
1961
union byte_def g0tpr6_addr;
1962
#define     g0tpr6       g0tpr6_addr.byte
1963
1964
/*------------------------------------------------------
1965
    Group 0 time measurement prescaler register 7
1966
------------------------------------------------------*/
1967
union byte_def g0tpr7_addr;
1968
#define     g0tpr7       g0tpr7_addr.byte
1969
1970
/*------------------------------------------------------
1971
    Group 0 waveform generate control register 0
1972
------------------------------------------------------*/
1973
union byte_def g0pocr0_addr;
1974
#define     g0pocr0       g0pocr0_addr.byte
1975
1976
#define     mod0_g0pocr0        g0pocr0_addr.bit.b0
1977
#define     mod1_g0pocr0        g0pocr0_addr.bit.b1
1978
#define     mod2_g0pocr0        g0pocr0_addr.bit.b2
1979
#define     ivl_g0pocr0         g0pocr0_addr.bit.b4
1980
#define     rld_g0pocr0         g0pocr0_addr.bit.b5
1981
#define     inv_g0pocr0         g0pocr0_addr.bit.b7
1982
1983
/*------------------------------------------------------
1984
    Group 0 waveform generate control register 1
1985
------------------------------------------------------*/
1986
union byte_def g0pocr1_addr;
1987
#define     g0pocr1       g0pocr1_addr.byte
1988
1989
#define     mod0_g0pocr1        g0pocr1_addr.bit.b0
1990
#define     mod1_g0pocr1        g0pocr1_addr.bit.b1
1991
#define     mod2_g0pocr1        g0pocr1_addr.bit.b2
1992
#define     ivl_g0pocr1         g0pocr1_addr.bit.b4
1993
#define     rld_g0pocr1         g0pocr1_addr.bit.b5
1994
#define     inv_g0pocr1         g0pocr1_addr.bit.b7
1995
1996
1997
/*------------------------------------------------------
1998
    Group 0 waveform generate control register 2
1999
------------------------------------------------------*/
2000
union byte_def g0pocr2_addr;
2001
#define     g0pocr2       g0pocr2_addr.byte
2002
2003
#define     mod0_g0pocr2        g0pocr2_addr.bit.b0
2004
#define     mod1_g0pocr2        g0pocr2_addr.bit.b1
2005
#define     mod2_g0pocr2        g0pocr2_addr.bit.b2
2006
#define     ivl_g0pocr2         g0pocr2_addr.bit.b4
2007
#define     rld_g0pocr2         g0pocr2_addr.bit.b5
2008
#define     inv_g0pocr2         g0pocr2_addr.bit.b7
2009
2010
2011
/*------------------------------------------------------
2012
    Group 0 waveform generate control register 3
2013
------------------------------------------------------*/
2014
union byte_def g0pocr3_addr;
2015
#define     g0pocr3       g0pocr3_addr.byte
2016
2017
#define     mod0_g0pocr3        g0pocr3_addr.bit.b0
2018
#define     mod1_g0pocr3        g0pocr3_addr.bit.b1
2019
#define     mod2_g0pocr3        g0pocr3_addr.bit.b2
2020
#define     ivl_g0pocr3         g0pocr3_addr.bit.b4
2021
#define     rld_g0pocr3         g0pocr3_addr.bit.b5
2022
#define     inv_g0pocr3         g0pocr3_addr.bit.b7
2023
2024
2025
/*------------------------------------------------------
2026
    Group 0 waveform generate control register 4
2027
------------------------------------------------------*/
2028
union byte_def g0pocr4_addr;
2029
#define     g0pocr4       g0pocr4_addr.byte
2030
2031
#define     mod0_g0pocr4        g0pocr4_addr.bit.b0
2032
#define     mod1_g0pocr4        g0pocr4_addr.bit.b1
2033
#define     mod2_g0pocr4        g0pocr4_addr.bit.b2
2034
#define     ivl_g0pocr4         g0pocr4_addr.bit.b4
2035
#define     rld_g0pocr4         g0pocr4_addr.bit.b5
2036
#define     inv_g0pocr4         g0pocr4_addr.bit.b7
2037
2038
2039
/*------------------------------------------------------
2040
    Group 0 waveform generate control register 5
2041
------------------------------------------------------*/
2042
union byte_def g0pocr5_addr;
2043
#define     g0pocr5       g0pocr5_addr.byte
2044
2045
#define     mod0_g0pocr5        g0pocr5_addr.bit.b0
2046
#define     mod1_g0pocr5        g0pocr5_addr.bit.b1
2047
#define     mod2_g0pocr5        g0pocr5_addr.bit.b2
2048
#define     ivl_g0pocr5         g0pocr5_addr.bit.b4
2049
#define     rld_g0pocr5         g0pocr5_addr.bit.b5
2050
#define     inv_g0pocr5         g0pocr5_addr.bit.b7
2051
2052
/*------------------------------------------------------
2053
    Group 0 waveform generate control register 6
2054
------------------------------------------------------*/
2055
union byte_def g0pocr6_addr;
2056
#define     g0pocr6       g0pocr6_addr.byte
2057
2058
#define     mod0_g0pocr6        g0pocr6_addr.bit.b0
2059
#define     mod1_g0pocr6        g0pocr6_addr.bit.b1
2060
#define     mod2_g0pocr6        g0pocr6_addr.bit.b2
2061
#define     ivl_g0pocr6         g0pocr6_addr.bit.b4
2062
#define     rld_g0pocr6         g0pocr6_addr.bit.b5
2063
#define     inv_g0pocr6         g0pocr6_addr.bit.b7
2064
2065
2066
/*------------------------------------------------------
2067
    Group 0 waveform generate control register 7
2068
------------------------------------------------------*/
2069
union byte_def g0pocr7_addr;
2070
#define     g0pocr7       g0pocr7_addr.byte
2071
2072
#define     mod0_g0pocr7        g0pocr7_addr.bit.b0
2073
#define     mod1_g0pocr7        g0pocr7_addr.bit.b1
2074
#define     mod2_g0pocr7        g0pocr7_addr.bit.b2
2075
#define     ivl_g0pocr7         g0pocr7_addr.bit.b4
2076
#define     rld_g0pocr7         g0pocr7_addr.bit.b5
2077
#define     inv_g0pocr7         g0pocr7_addr.bit.b7
2078
2079
2080
/*------------------------------------------------------
2081
    Group 0 function select register
2082
------------------------------------------------------*/
2083
union byte_def g0fs_addr;
2084
#define     g0fs       g0fs_addr.byte
2085
2086
#define     fsc0_g0fs          g0fs_addr.bit.b0
2087
#define     fsc1_g0fs          g0fs_addr.bit.b1
2088
#define     fsc2_g0fs          g0fs_addr.bit.b2
2089
#define     fsc3_g0fs          g0fs_addr.bit.b3
2090
#define     fsc4_g0fs          g0fs_addr.bit.b4
2091
#define     fsc5_g0fs          g0fs_addr.bit.b5
2092
#define     fsc6_g0fs          g0fs_addr.bit.b6
2093
#define     fsc7_g0fs          g0fs_addr.bit.b7
2094
2095
/*------------------------------------------------------
2096
    Group 0 function enable register
2097
------------------------------------------------------*/
2098
union byte_def g0fe_addr;
2099
#define     g0fe       g0fe_addr.byte
2100
2101
#define     ife0_g0fe          g0fe_addr.bit.b0
2102
#define     ife1_g0fe          g0fe_addr.bit.b1
2103
#define     ife2_g0fe          g0fe_addr.bit.b2
2104
#define     ife3_g0fe          g0fe_addr.bit.b3
2105
#define     ife4_g0fe          g0fe_addr.bit.b4
2106
#define     ife5_g0fe          g0fe_addr.bit.b5
2107
#define     ife6_g0fe          g0fe_addr.bit.b6
2108
#define     ife7_g0fe          g0fe_addr.bit.b7
2109
2110
/*------------------------------------------------------
2111
    Group 0 SI/O communication mode register
2112
------------------------------------------------------*/
2113
union byte_def g0mr_addr;
2114
#define     g0mr       g0mr_addr.byte
2115
2116
#define     gmd0_g0mr          g0mr_addr.bit.b0
2117
#define     gmd1_g0mr          g0mr_addr.bit.b1
2118
#define     ckdir_g0mr         g0mr_addr.bit.b2
2119
#define     stps_g0mr          g0mr_addr.bit.b3
2120
//#define     pry_g0mr           g0mr_addr.bit.b4
2121
//#define     prye_g0mr          g0mr_addr.bit.b5
2122
#define     uform_g0mr         g0mr_addr.bit.b6
2123
#define     irs_g0mr           g0mr_addr.bit.b7
2124
2125
/*------------------------------------------------------
2126
    Group 0 SI/O communication control register
2127
------------------------------------------------------*/
2128
union byte_def g0cr_addr;
2129
#define     g0cr       g0cr_addr.byte
2130
2131
#define     ti_g0cr             g0cr_addr.bit.b0
2132
#define     txept_g0cr          g0cr_addr.bit.b1
2133
#define     ri_g0cr             g0cr_addr.bit.b2
2134
#define     te_g0cr             g0cr_addr.bit.b4
2135
#define     re_g0cr             g0cr_addr.bit.b5
2136
#define     ipol_g0cr           g0cr_addr.bit.b6
2137
#define     opol_g0cr           g0cr_addr.bit.b7
2138
2139
/*------------------------------------------------------
2140
    Group 0 SI/O expansion mode register
2141
------------------------------------------------------*/
2142
union byte_def g0emr_addr;
2143
#define     g0emr       g0emr_addr.byte
2144
2145
#define     smode_g0emr         g0emr_addr.bit.b0
2146
#define     crcv_g0emr          g0emr_addr.bit.b1
2147
#define     acrc_g0emr          g0emr_addr.bit.b2
2148
#define     bsint_g0emr         g0emr_addr.bit.b3
2149
#define     rxsl_g0emr          g0emr_addr.bit.b4
2150
#define     txsl_g0emr          g0emr_addr.bit.b5
2151
#define     crc0_g0emr          g0emr_addr.bit.b6
2152
#define     crc1_g0emr          g0emr_addr.bit.b7
2153
2154
/*------------------------------------------------------
2155
    Group 0 SI/O expansion transmit control register
2156
------------------------------------------------------*/
2157
union byte_def g0etc_addr;
2158
#define     g0etc       g0etc_addr.byte
2159
2160
#define     sof_g0etc         g0etc_addr.bit.b3
2161
#define     tcrce_g0etc       g0etc_addr.bit.b4
2162
#define     abte_g0etc        g0etc_addr.bit.b5
2163
#define     tbsf0_g0etc       g0etc_addr.bit.b6
2164
#define     tbsf1_g0etc       g0etc_addr.bit.b7
2165
2166
/*------------------------------------------------------
2167
    Group 0 SI/O communication mode register
2168
------------------------------------------------------*/
2169
union byte_def g0erc_addr;
2170
#define     g0erc       g0erc_addr.byte
2171
2172
#define     cmp0e_g0erc       g0erc_addr.bit.b0
2173
#define     cmp1e_g0erc       g0erc_addr.bit.b1
2174
#define     cmp2e_g0erc       g0erc_addr.bit.b2
2175
#define     cmp3e_g0erc       g0erc_addr.bit.b3
2176
#define     rcrce_g0erc       g0erc_addr.bit.b4
2177
#define     rshte_g0erc       g0erc_addr.bit.b5
2178
#define     rbsf0_g0erc       g0erc_addr.bit.b6
2179
#define     rbsf1_g0erc       g0erc_addr.bit.b7
2180
2181
/*------------------------------------------------------
2182
    Group 0 SI/O special communication
2183
            interrupt detect register
2184
------------------------------------------------------*/
2185
union byte_def g0irf_addr;
2186
#define     g0irf       g0irf_addr.byte
2187
2188
#define     bserr_g0irf       g0irf_addr.bit.b2
2189
#define     abt_g0irf         g0irf_addr.bit.b3
2190
#define     irf0_g0irf        g0irf_addr.bit.b4
2191
#define     irf1_g0irf        g0irf_addr.bit.b5
2192
#define     irf2_g0irf        g0irf_addr.bit.b6
2193
#define     irf3_g0irf        g0irf_addr.bit.b7
2194
2195
/*------------------------------------------------------
2196
    Group 0 receive data register
2197
------------------------------------------------------*/
2198
/* union byte_def g0dr_addr;
2199
#define     g0dr       g0dr_addr.byte
2200
*/
2201
2202
/*------------------------------------------------------
2203
    Group 0 transmitting buffer register
2204
------------------------------------------------------*/
2205
union byte_def g0tb_addr;
2206
#define     g0tb       g0tb_addr.byte
2207
2208
/*------------------------------------------------------
2209
    Group 0 data compare register 0
2210
------------------------------------------------------*/
2211
union byte_def g0cmp0_addr;
2212
#define     g0cmp0       g0cmp0_addr.byte
2213
2214
/*------------------------------------------------------
2215
    Group 0 data compare register 1
2216
------------------------------------------------------*/
2217
union byte_def g0cmp1_addr;
2218
#define     g0cmp1       g0cmp1_addr.byte
2219
2220
/*------------------------------------------------------
2221
    Group 0 data compare register 2
2222
------------------------------------------------------*/
2223
union byte_def g0cmp2_addr;
2224
#define     g0cmp2       g0cmp2_addr.byte
2225
2226
/*------------------------------------------------------
2227
    Group 0 data compare register 3
2228
------------------------------------------------------*/
2229
union byte_def g0cmp3_addr;
2230
#define     g0cmp3       g0cmp3_addr.byte
2231
2232
/*------------------------------------------------------
2233
    Group 0 data mask register 0
2234
------------------------------------------------------*/
2235
union byte_def g0msk0_addr;
2236
#define     g0msk0       g0msk0_addr.byte
2237
2238
/*------------------------------------------------------
2239
    Group 0 data mask register 1
2240
------------------------------------------------------*/
2241
union byte_def g0msk1_addr;
2242
#define     g0msk1       g0msk1_addr.byte
2243
2244
/*------------------------------------------------------
2245
    Group 0 transmit output register
2246
------------------------------------------------------*/
2247
union byte_def g0to_addr;
2248
#define     g0to       g0to_addr.byte
2249
2250
/*------------------------------------------------------
2251
    Group 0 receive input register
2252
------------------------------------------------------*/
2253
union byte_def g0ri_addr;
2254
#define     g0ri       g0ri_addr.byte
2255
2256
/*------------------------------------------------------
2257
    Group 1 base timer control register 0
2258
------------------------------------------------------*/
2259
union byte_def g1bcr0_addr;
2260
#define     g1bcr0       g1bcr0_addr.byte
2261
2262
#define     bck0_g1bcr0        g1bcr0_addr.bit.b0
2263
#define     bck1_g1bcr0        g1bcr0_addr.bit.b1
2264
#define     div0_g1bcr0        g1bcr0_addr.bit.b2
2265
#define     div1_g1bcr0        g1bcr0_addr.bit.b3
2266
#define     div2_g1bcr0        g1bcr0_addr.bit.b4
2267
#define     div3_g1bcr0        g1bcr0_addr.bit.b5
2268
#define     div4_g1bcr0        g1bcr0_addr.bit.b6
2269
#define     it_g1bcr0          g1bcr0_addr.bit.b7
2270
2271
/*------------------------------------------------------
2272
    Group 1 base timer control register 1
2273
------------------------------------------------------*/
2274
union byte_def g1bcr1_addr;
2275
#define     g1bcr1       g1bcr1_addr.byte
2276
2277
#define     rst0_g1bcr1        g1bcr1_addr.bit.b0
2278
#define     rst1_g1bcr1        g1bcr1_addr.bit.b1
2279
#define     rst2_g1bcr1        g1bcr1_addr.bit.b2
2280
#define                rst3_g1bcr1                   g1bcr1_addr.bit.b3
2281
#define     bts_g1bcr1         g1bcr1_addr.bit.b4
2282
#define     ud0_g1bcr1         g1bcr1_addr.bit.b5
2283
#define     ud1_g1bcr1         g1bcr1_addr.bit.b6
2284
#define     cas_g1bcr1         g1bcr1_addr.bit.b7
2285
2286
/*------------------------------------------------------
2287
    Group 1 time measurement control register 0
2288
------------------------------------------------------*/
2289
union byte_def g1tmcr0_addr;
2290
#define     g1tmcr0       g1tmcr0_addr.byte
2291
2292
#define     cts0_g1tmcr0      g1tmcr0_addr.bit.b0
2293
#define     cts1_g1tmcr0      g1tmcr0_addr.bit.b1
2294
#define     df0_g1tmcr0       g1tmcr0_addr.bit.b2
2295
#define     df1_g1tmcr0       g1tmcr0_addr.bit.b3
2296
#define     gt_g1tmcr0        g1tmcr0_addr.bit.b4
2297
#define     goc_g1tmcr0       g1tmcr0_addr.bit.b5
2298
#define     gsc_g1tmcr0       g1tmcr0_addr.bit.b6
2299
#define     pr_g1tmcr0        g1tmcr0_addr.bit.b7
2300
2301
2302
/*------------------------------------------------------
2303
    Group 1 time measurement control register 1
2304
------------------------------------------------------*/
2305
union byte_def g1tmcr1_addr;
2306
#define     g1tmcr1       g1tmcr1_addr.byte
2307
2308
#define     cts0_g1tmcr1      g1tmcr1_addr.bit.b0
2309
#define     cts1_g1tmcr1      g1tmcr1_addr.bit.b1
2310
#define     df0_g1tmcr1       g1tmcr1_addr.bit.b2
2311
#define     df1_g1tmcr1       g1tmcr1_addr.bit.b3
2312
#define     gt_g1tmcr1        g1tmcr1_addr.bit.b4
2313
#define     goc_g1tmcr1       g1tmcr1_addr.bit.b5
2314
#define     gsc_g1tmcr1       g1tmcr1_addr.bit.b6
2315
#define     pr_g1tmcr1        g1tmcr1_addr.bit.b7
2316
2317
/*------------------------------------------------------
2318
    Group 1 time measurement control register 2
2319
------------------------------------------------------*/
2320
union byte_def g1tmcr2_addr;
2321
#define     g1tmcr2       g1tmcr2_addr.byte
2322
2323
#define     cts0_g1tmcr2      g1tmcr2_addr.bit.b0
2324
#define     cts1_g1tmcr2      g1tmcr2_addr.bit.b1
2325
#define     df0_g1tmcr2       g1tmcr2_addr.bit.b2
2326
#define     df1_g1tmcr2       g1tmcr2_addr.bit.b3
2327
#define     gt_g1tmcr2        g1tmcr2_addr.bit.b4
2328
#define     goc_g1tmcr2       g1tmcr2_addr.bit.b5
2329
#define     gsc_g1tmcr2       g1tmcr2_addr.bit.b6
2330
#define     pr_g1tmcr2        g1tmcr2_addr.bit.b7
2331
2332
/*------------------------------------------------------
2333
    Group 1 time measurement control register 3
2334
------------------------------------------------------*/
2335
union byte_def g1tmcr3_addr;
2336
#define     g1tmcr3       g1tmcr3_addr.byte
2337
2338
#define     cts0_g1tmcr3      g1tmcr3_addr.bit.b0
2339
#define     cts1_g1tmcr3      g1tmcr3_addr.bit.b1
2340
#define     df0_g1tmcr3       g1tmcr3_addr.bit.b2
2341
#define     df1_g1tmcr3       g1tmcr3_addr.bit.b3
2342
#define     gt_g1tmcr3        g1tmcr3_addr.bit.b4
2343
#define     goc_g1tmcr3       g1tmcr3_addr.bit.b5
2344
#define     gsc_g1tmcr3       g1tmcr3_addr.bit.b6
2345
#define     pr_g1tmcr3        g1tmcr3_addr.bit.b7
2346
2347
2348
/*------------------------------------------------------
2349
    Group 1 time measurement control register 4
2350
------------------------------------------------------*/
2351
union byte_def g1tmcr4_addr;
2352
#define     g1tmcr4       g1tmcr4_addr.byte
2353
2354
#define     cts0_g1tmcr4      g1tmcr4_addr.bit.b0
2355
#define     cts1_g1tmcr4      g1tmcr4_addr.bit.b1
2356
#define     df0_g1tmcr4       g1tmcr4_addr.bit.b2
2357
#define     df1_g1tmcr4       g1tmcr4_addr.bit.b3
2358
#define     gt_g1tmcr4        g1tmcr4_addr.bit.b4
2359
#define     goc_g1tmcr4       g1tmcr4_addr.bit.b5
2360
#define     gsc_g1tmcr4       g1tmcr4_addr.bit.b6
2361
#define     pr_g1tmcr4        g1tmcr4_addr.bit.b7
2362
2363
2364
/*------------------------------------------------------
2365
    Group 1 time measurement control register 5
2366
------------------------------------------------------*/
2367
union byte_def g1tmcr5_addr;
2368
#define     g1tmcr5       g1tmcr5_addr.byte
2369
2370
#define     cts0_g1tmcr5      g1tmcr5_addr.bit.b0
2371
#define     cts1_g1tmcr5      g1tmcr5_addr.bit.b1
2372
#define     df0_g1tmcr5       g1tmcr5_addr.bit.b2
2373
#define     df1_g1tmcr5       g1tmcr5_addr.bit.b3
2374
#define     gt_g1tmcr5        g1tmcr5_addr.bit.b4
2375
#define     goc_g1tmcr5       g1tmcr5_addr.bit.b5
2376
#define     gsc_g1tmcr5       g1tmcr5_addr.bit.b6
2377
#define     pr_g1tmcr5        g1tmcr5_addr.bit.b7
2378
2379
2380
/*------------------------------------------------------
2381
    Group 1 time measurement control register 6
2382
------------------------------------------------------*/
2383
union byte_def g1tmcr6_addr;
2384
#define     g1tmcr6       g1tmcr6_addr.byte
2385
2386
#define     cts0_g1tmcr6      g1tmcr6_addr.bit.b0
2387
#define     cts1_g1tmcr6      g1tmcr6_addr.bit.b1
2388
#define     df0_g1tmcr6       g1tmcr6_addr.bit.b2
2389
#define     df1_g1tmcr6       g1tmcr6_addr.bit.b3
2390
#define     gt_g1tmcr6        g1tmcr6_addr.bit.b4
2391
#define     goc_g1tmcr6       g1tmcr6_addr.bit.b5
2392
#define     gsc_g1tmcr6       g1tmcr6_addr.bit.b6
2393
#define     pr_g1tmcr6        g1tmcr6_addr.bit.b7
2394
2395
/*------------------------------------------------------
2396
    Group 1 time measurement control register 7
2397
------------------------------------------------------*/
2398
union byte_def g1tmcr7_addr;
2399
#define     g1tmcr7       g1tmcr7_addr.byte
2400
2401
#define     cts0_g1tmcr7      g1tmcr7_addr.bit.b0
2402
#define     cts1_g1tmcr7      g1tmcr7_addr.bit.b1
2403
#define     df0_g1tmcr7       g1tmcr7_addr.bit.b2
2404
#define     df1_g1tmcr7       g1tmcr7_addr.bit.b3
2405
#define     gt_g1tmcr7        g1tmcr7_addr.bit.b4
2406
#define     goc_g1tmcr7       g1tmcr7_addr.bit.b5
2407
#define     gsc_g1tmcr7       g1tmcr7_addr.bit.b6
2408
#define     pr_g1tmcr7        g1tmcr7_addr.bit.b7
2409
2410
/*------------------------------------------------------
2411
    Group 1 time measurement prescaler register 6
2412
------------------------------------------------------*/
2413
union byte_def g1tpr6_addr;
2414
#define     g1tpr6       g1tpr6_addr.byte
2415
2416
/*------------------------------------------------------
2417
    Group 1 time measurement prescaler register 7
2418
------------------------------------------------------*/
2419
union byte_def g1tpr7_addr;
2420
#define     g1tpr7       g1tpr7_addr.byte
2421
2422
/*------------------------------------------------------
2423
    Group 1 waveform generate control register 0
2424
------------------------------------------------------*/
2425
union byte_def g1pocr0_addr;
2426
#define     g1pocr0       g1pocr0_addr.byte
2427
2428
#define     mod0_g1pocr0        g1pocr0_addr.bit.b0
2429
#define     mod1_g1pocr0        g1pocr0_addr.bit.b1
2430
#define     mod2_g1pocr0        g1pocr0_addr.bit.b2
2431
#define     ivl_g1pocr0         g1pocr0_addr.bit.b4
2432
#define     rld_g1pocr0         g1pocr0_addr.bit.b5
2433
#define     inv_g1pocr0         g1pocr0_addr.bit.b7
2434
2435
/*------------------------------------------------------
2436
    Group 1 waveform generate control register 1
2437
------------------------------------------------------*/
2438
union byte_def g1pocr1_addr;
2439
#define     g1pocr1       g1pocr1_addr.byte
2440
2441
#define     mod0_g1pocr1        g1pocr1_addr.bit.b0
2442
#define     mod1_g1pocr1        g1pocr1_addr.bit.b1
2443
#define     mod2_g1pocr1        g1pocr1_addr.bit.b2
2444
#define     ivl_g1pocr1         g1pocr1_addr.bit.b4
2445
#define     rld_g1pocr1         g1pocr1_addr.bit.b5
2446
#define     inv_g1pocr1         g1pocr1_addr.bit.b7
2447
2448
2449
/*------------------------------------------------------
2450
    Group 1 waveform generate control register 2
2451
------------------------------------------------------*/
2452
union byte_def g1pocr2_addr;
2453
#define     g1pocr2       g1pocr2_addr.byte
2454
2455
#define     mod0_g1pocr2        g1pocr2_addr.bit.b0
2456
#define     mod1_g1pocr2        g1pocr2_addr.bit.b1
2457
#define     mod2_g1pocr2        g1pocr2_addr.bit.b2
2458
#define     ivl_g1pocr2         g1pocr2_addr.bit.b4
2459
#define     rld_g1pocr2         g1pocr2_addr.bit.b5
2460
#define     inv_g1pocr2         g1pocr2_addr.bit.b7
2461
2462
/*------------------------------------------------------
2463
    Group 1 waveform generate control register 3
2464
------------------------------------------------------*/
2465
union byte_def g1pocr3_addr;
2466
#define     g1pocr3       g1pocr3_addr.byte
2467
2468
#define     mod0_g1pocr3        g1pocr3_addr.bit.b0
2469
#define     mod1_g1pocr3        g1pocr3_addr.bit.b1
2470
#define     mod2_g1pocr3        g1pocr3_addr.bit.b2
2471
#define     ivl_g1pocr3         g1pocr3_addr.bit.b4
2472
#define     rld_g1pocr3         g1pocr3_addr.bit.b5
2473
#define     inv_g1pocr3         g1pocr3_addr.bit.b7
2474
2475
2476
/*------------------------------------------------------
2477
    Group 1 waveform generate control register 4
2478
------------------------------------------------------*/
2479
union byte_def g1pocr4_addr;
2480
#define     g1pocr4       g1pocr4_addr.byte
2481
2482
#define     mod0_g1pocr4        g1pocr4_addr.bit.b0
2483
#define     mod1_g1pocr4        g1pocr4_addr.bit.b1
2484
#define     mod2_g1pocr4        g1pocr4_addr.bit.b2
2485
#define     ivl_g1pocr4         g1pocr4_addr.bit.b4
2486
#define     rld_g1pocr4         g1pocr4_addr.bit.b5
2487
#define     inv_g1pocr4         g1pocr4_addr.bit.b7
2488
2489
2490
/*------------------------------------------------------
2491
    Group 1 waveform generate control register 5
2492
------------------------------------------------------*/
2493
union byte_def g1pocr5_addr;
2494
#define     g1pocr5       g1pocr5_addr.byte
2495
2496
#define     mod0_g1pocr5        g1pocr5_addr.bit.b0
2497
#define     mod1_g1pocr5        g1pocr5_addr.bit.b1
2498
#define     mod2_g1pocr5        g1pocr5_addr.bit.b2
2499
#define     ivl_g1pocr5         g1pocr5_addr.bit.b4
2500
#define     rld_g1pocr5         g1pocr5_addr.bit.b5
2501
#define     inv_g1pocr5         g1pocr5_addr.bit.b7
2502
2503
/*------------------------------------------------------
2504
    Group 1 waveform generate control register 6
2505
------------------------------------------------------*/
2506
union byte_def g1pocr6_addr;
2507
#define     g1pocr6       g1pocr6_addr.byte
2508
2509
#define     mod0_g1pocr6        g1pocr6_addr.bit.b0
2510
#define     mod1_g1pocr6        g1pocr6_addr.bit.b1
2511
#define     mod2_g1pocr6        g1pocr6_addr.bit.b2
2512
#define     ivl_g1pocr6         g1pocr6_addr.bit.b4
2513
#define     rld_g1pocr6         g1pocr6_addr.bit.b5
2514
#define     inv_g1pocr6         g1pocr6_addr.bit.b7
2515
2516
/*------------------------------------------------------
2517
    Group 1 waveform generate control register 7
2518
------------------------------------------------------*/
2519
union byte_def g1pocr7_addr;
2520
#define     g1pocr7       g1pocr7_addr.byte
2521
2522
#define     mod0_g1pocr7        g1pocr7_addr.bit.b0
2523
#define     mod1_g1pocr7        g1pocr7_addr.bit.b1
2524
#define     mod2_g1pocr7        g1pocr7_addr.bit.b2
2525
#define     ivl_g1pocr7         g1pocr7_addr.bit.b4
2526
#define     rld_g1pocr7         g1pocr7_addr.bit.b5
2527
#define     inv_g1pocr7         g1pocr7_addr.bit.b7
2528
2529
/*------------------------------------------------------
2530
    Group 1 function select register
2531
------------------------------------------------------*/
2532
union byte_def g1fs_addr;
2533
#define     g1fs       g1fs_addr.byte
2534
2535
#define     fsc0_g1fs          g1fs_addr.bit.b0
2536
#define     fsc1_g1fs          g1fs_addr.bit.b1
2537
#define     fsc2_g1fs          g1fs_addr.bit.b2
2538
#define     fsc3_g1fs          g1fs_addr.bit.b3
2539
#define     fsc4_g1fs          g1fs_addr.bit.b4
2540
#define     fsc5_g1fs          g1fs_addr.bit.b5
2541
#define     fsc6_g1fs          g1fs_addr.bit.b6
2542
#define     fsc7_g1fs          g1fs_addr.bit.b7
2543
2544
/*------------------------------------------------------
2545
    Group 1 function enable register
2546
------------------------------------------------------*/
2547
union byte_def g1fe_addr;
2548
#define     g1fe       g1fe_addr.byte
2549
2550
#define     ife0_g1fe          g1fe_addr.bit.b0
2551
#define     ife1_g1fe          g1fe_addr.bit.b1
2552
#define     ife2_g1fe          g1fe_addr.bit.b2
2553
#define     ife3_g1fe          g1fe_addr.bit.b3
2554
#define     ife4_g1fe          g1fe_addr.bit.b4
2555
#define     ife5_g1fe          g1fe_addr.bit.b5
2556
#define     ife6_g1fe          g1fe_addr.bit.b6
2557
#define     ife7_g1fe          g1fe_addr.bit.b7
2558
2559
/*------------------------------------------------------
2560
    Group 1 SI/O communication mode register
2561
------------------------------------------------------*/
2562
union byte_def g1mr_addr;
2563
#define     g1mr       g1mr_addr.byte
2564
2565
#define     gmd0_g1mr          g1mr_addr.bit.b0
2566
#define     gmd1_g1mr          g1mr_addr.bit.b1
2567
#define     ckdir_g1mr         g1mr_addr.bit.b2
2568
#define     stps_g1mr          g1mr_addr.bit.b3
2569
//#define     pry_g1mr           g1mr_addr.bit.b4
2570
//#define     prye_g1mr          g1mr_addr.bit.b5
2571
#define     uform_g1mr         g1mr_addr.bit.b6
2572
#define     irs_g1mr           g1mr_addr.bit.b7
2573
2574
/*------------------------------------------------------
2575
    Group 1 SI/O communication control register
2576
------------------------------------------------------*/
2577
union byte_def g1cr_addr;
2578
#define     g1cr       g1cr_addr.byte
2579
2580
#define     ti_g1cr             g1cr_addr.bit.b0
2581
#define     txept_g1cr          g1cr_addr.bit.b1
2582
#define     ri_g1cr             g1cr_addr.bit.b2
2583
#define     te_g1cr             g1cr_addr.bit.b4
2584
#define     re_g1cr             g1cr_addr.bit.b5
2585
#define     ipol_g1cr           g1cr_addr.bit.b6
2586
#define     opol_g1cr           g1cr_addr.bit.b7
2587
2588
/*------------------------------------------------------
2589
    Group 1 SI/O expansion mode register
2590
------------------------------------------------------*/
2591
union byte_def g1emr_addr;
2592
#define     g1emr       g1emr_addr.byte
2593
2594
#define     smode_g1emr         g1emr_addr.bit.b0
2595
#define     crcv_g1emr          g1emr_addr.bit.b1
2596
#define     acrc_g1emr          g1emr_addr.bit.b2
2597
#define     bsint_g1emr         g1emr_addr.bit.b3
2598
#define     rxsl_g1emr          g1emr_addr.bit.b4
2599
#define     txsl_g1emr          g1emr_addr.bit.b5
2600
#define     crc0_g1emr          g1emr_addr.bit.b6
2601
#define     crc1_g1emr          g1emr_addr.bit.b7
2602
2603
/*------------------------------------------------------
2604
    Group 1 SI/O expansion transmit control register
2605
------------------------------------------------------*/
2606
union byte_def g1etc_addr;
2607
#define     g1etc       g1etc_addr.byte
2608
2609
#define     sof_g1etc         g1etc_addr.bit.b3
2610
#define     tcrce_g1etc       g1etc_addr.bit.b4
2611
#define     abte_g1etc        g1etc_addr.bit.b5
2612
#define     tbsf0_g1etc       g1etc_addr.bit.b6
2613
#define     tbsf1_g1etc       g1etc_addr.bit.b7
2614
2615
/*------------------------------------------------------
2616
    Group 1 SI/O communication mode register
2617
------------------------------------------------------*/
2618
union byte_def g1erc_addr;
2619
#define     g1erc       g1erc_addr.byte
2620
2621
#define     cmp0e_g1erc       g1erc_addr.bit.b0
2622
#define     cmp1e_g1erc       g1erc_addr.bit.b1
2623
#define     cmp2e_g1erc       g1erc_addr.bit.b2
2624
#define     cmp3e_g1erc       g1erc_addr.bit.b3
2625
#define     rcrce_g1erc       g1erc_addr.bit.b4
2626
#define     rshte_g1erc       g1erc_addr.bit.b5
2627
#define     rbsf0_g1erc       g1erc_addr.bit.b6
2628
#define     rbsf1_g1erc       g1erc_addr.bit.b7
2629
2630
/*------------------------------------------------------
2631
    Group 1 SI/O special communication
2632
            interrupt detect register
2633
------------------------------------------------------*/
2634
union byte_def g1irf_addr;
2635
#define     g1irf       g1irf_addr.byte
2636
2637
#define     bserr_g1irf       g1irf_addr.bit.b2
2638
#define     abt_g1irf         g1irf_addr.bit.b3
2639
#define     irf0_g1irf        g1irf_addr.bit.b4
2640
#define     irf1_g1irf        g1irf_addr.bit.b5
2641
#define     irf2_g1irf        g1irf_addr.bit.b6
2642
#define     irf3_g1irf        g1irf_addr.bit.b7
2643
2644
/*------------------------------------------------------
2645
    Group 1 receive data register
2646
------------------------------------------------------*/
2647
/* union byte_def g1dr_addr;
2648
#define     g1dr       g1dr_addr.byte
2649
*/
2650
2651
/*------------------------------------------------------
2652
    Group 1 SI/O transmitting buffer register
2653
------------------------------------------------------*/
2654
union byte_def g1tb_addr;
2655
#define     g1tb       g1tb_addr.byte
2656
2657
/*------------------------------------------------------
2658
    Group 1 data compare register 0
2659
------------------------------------------------------*/
2660
union byte_def g1cmp0_addr;
2661
#define     g1cmp0       g1cmp0_addr.byte
2662
2663
/*------------------------------------------------------
2664
    Group 1 data compare register 1
2665
------------------------------------------------------*/
2666
union byte_def g1cmp1_addr;
2667
#define     g1cmp1       g1cmp1_addr.byte
2668
2669
/*------------------------------------------------------
2670
    Group 1 data compare register 2
2671
------------------------------------------------------*/
2672
union byte_def g1cmp2_addr;
2673
#define     g1cmp2       g1cmp2_addr.byte
2674
2675
/*------------------------------------------------------
2676
    Group 1 data compare register 3
2677
------------------------------------------------------*/
2678
union byte_def g1cmp3_addr;
2679
#define     g1cmp3       g1cmp3_addr.byte
2680
2681
/*------------------------------------------------------
2682
    Group 1 data mask register 0
2683
------------------------------------------------------*/
2684
union byte_def g1msk0_addr;
2685
#define     g1msk0       g1msk0_addr.byte
2686
2687
/*------------------------------------------------------
2688
    Group 1 data mask register 1
2689
------------------------------------------------------*/
2690
union byte_def g1msk1_addr;
2691
#define     g1msk1       g1msk1_addr.byte
2692
2693
/*------------------------------------------------------
2694
    Group 1 transmit output register
2695
------------------------------------------------------*/
2696
union byte_def g1to_addr;
2697
#define     g1to       g1to_addr.byte
2698
2699
/*------------------------------------------------------
2700
    Group 1 receive input register
2701
------------------------------------------------------*/
2702
union byte_def g1ri_addr;
2703
#define     g1ri       g1ri_addr.byte
2704
2705
2706
/*------------------------------------------------------
2707
    Group 2 base timer control register 0
2708
------------------------------------------------------*/
2709
union byte_def g2bcr0_addr;
2710
#define     g2bcr0       g2bcr0_addr.byte
2711
2712
#define     bck0_g2bcr0        g2bcr0_addr.bit.b0
2713
#define     bck1_g2bcr0        g2bcr0_addr.bit.b1
2714
#define     div0_g2bcr0        g2bcr0_addr.bit.b2
2715
#define     div1_g2bcr0        g2bcr0_addr.bit.b3
2716
#define     div2_g2bcr0        g2bcr0_addr.bit.b4
2717
#define     div3_g2bcr0        g2bcr0_addr.bit.b5
2718
#define     div4_g2bcr0        g2bcr0_addr.bit.b6
2719
#define     it_g2bcr0          g2bcr0_addr.bit.b7
2720
2721
/*------------------------------------------------------
2722
    Group 2 base timer control register 1
2723
------------------------------------------------------*/
2724
union byte_def g2bcr1_addr;
2725
#define     g2bcr1       g2bcr1_addr.byte
2726
2727
#define     rst0_g2bcr1        g2bcr1_addr.bit.b0
2728
#define     rst1_g2bcr1        g2bcr1_addr.bit.b1
2729
#define     rst2_g2bcr1        g2bcr1_addr.bit.b2
2730
//#define                rst3_g2bcr1                   g2bcr1_addr.bit.b3
2731
#define     bst_g2bcr1         g2bcr1_addr.bit.b4
2732
//#define                ud0_g2bcr1                   g2bcr1_addr.bit.b5
2733
//#define                ud1_g2bcr1                   g2bcr1_addr.bit.b6
2734
#define     prp_g2bcr1         g2bcr1_addr.bit.b7
2735
2736
/*------------------------------------------------------
2737
    Group 2 waveform generate control register 0
2738
------------------------------------------------------*/
2739
union byte_def g2pocr0_addr;
2740
#define     g2pocr0       g2pocr0_addr.byte
2741
2742
#define     mod0_g2pocr0        g2pocr0_addr.bit.b0
2743
#define     mod1_g2pocr0        g2pocr0_addr.bit.b1
2744
#define     mod2_g2pocr0        g2pocr0_addr.bit.b2
2745
#define     prt_g2pocr0         g2pocr0_addr.bit.b3
2746
#define     ivl_g2pocr0         g2pocr0_addr.bit.b4
2747
#define     rld_g2pocr0         g2pocr0_addr.bit.b5
2748
#define     rtp_g2pocr0         g2pocr0_addr.bit.b6
2749
#define     inv_g2pocr0         g2pocr0_addr.bit.b7
2750
2751
/*------------------------------------------------------
2752
    Group 2 waveform generate control register 1
2753
------------------------------------------------------*/
2754
union byte_def g2pocr1_addr;
2755
#define     g2pocr1       g2pocr1_addr.byte
2756
2757
#define     mod0_g2pocr1        g2pocr1_addr.bit.b0
2758
#define     mod1_g2pocr1        g2pocr1_addr.bit.b1
2759
#define     mod2_g2pocr1        g2pocr1_addr.bit.b2
2760
#define     prt_g2pocr1         g2pocr1_addr.bit.b3
2761
#define     ivl_g2pocr1         g2pocr1_addr.bit.b4
2762
#define     rld_g2pocr1         g2pocr1_addr.bit.b5
2763
#define     rtp_g2pocr1         g2pocr1_addr.bit.b6
2764
#define     inv_g2pocr1         g2pocr1_addr.bit.b7
2765
2766
/*------------------------------------------------------
2767
    Group 2 waveform generate control register 2
2768
------------------------------------------------------*/
2769
union byte_def g2pocr2_addr;
2770
#define     g2pocr2       g2pocr2_addr.byte
2771
2772
#define     mod0_g2pocr2        g2pocr2_addr.bit.b0
2773
#define     mod1_g2pocr2        g2pocr2_addr.bit.b1
2774
#define     mod2_g2pocr2        g2pocr2_addr.bit.b2
2775
#define     prt_g2pocr2         g2pocr2_addr.bit.b3
2776
#define     ivl_g2pocr2         g2pocr2_addr.bit.b4
2777
#define     rld_g2pocr2         g2pocr2_addr.bit.b5
2778
#define     rtp_g2pocr2         g2pocr2_addr.bit.b6
2779
#define     inv_g2pocr2         g2pocr2_addr.bit.b7
2780
2781
/*------------------------------------------------------
2782
    Group 2 waveform generate control register 3
2783
------------------------------------------------------*/
2784
union byte_def g2pocr3_addr;
2785
#define     g2pocr3       g2pocr3_addr.byte
2786
2787
#define     mod0_g2pocr3        g2pocr3_addr.bit.b0
2788
#define     mod1_g2pocr3        g2pocr3_addr.bit.b1
2789
#define     mod2_g2pocr3        g2pocr3_addr.bit.b2
2790
#define     prt_g2pocr3         g2pocr3_addr.bit.b3
2791
#define     ivl_g2pocr3         g2pocr3_addr.bit.b4
2792
#define     rld_g2pocr3         g2pocr3_addr.bit.b5
2793
#define     rtp_g2pocr3         g2pocr3_addr.bit.b6
2794
#define     inv_g2pocr3         g2pocr3_addr.bit.b7
2795
2796
/*------------------------------------------------------
2797
    Group 2 waveform generate control register 4
2798
------------------------------------------------------*/
2799
union byte_def g2pocr4_addr;
2800
#define     g2pocr4       g2pocr4_addr.byte
2801
2802
#define     mod0_g2pocr4        g2pocr4_addr.bit.b0
2803
#define     mod1_g2pocr4        g2pocr4_addr.bit.b1
2804
#define     mod2_g2pocr4        g2pocr4_addr.bit.b2
2805
#define     prt_g2pocr4         g2pocr4_addr.bit.b3
2806
#define     ivl_g2pocr4         g2pocr4_addr.bit.b4
2807
#define     rld_g2pocr4         g2pocr4_addr.bit.b5
2808
#define     rtp_g2pocr4         g2pocr4_addr.bit.b6
2809
#define     inv_g2pocr4         g2pocr4_addr.bit.b7
2810
2811
/*------------------------------------------------------
2812
    Group 2 waveform generate control register 5
2813
------------------------------------------------------*/
2814
union byte_def g2pocr5_addr;
2815
#define     g2pocr5       g2pocr5_addr.byte
2816
2817
#define     mod0_g2pocr5        g2pocr5_addr.bit.b0
2818
#define     mod1_g2pocr5        g2pocr5_addr.bit.b1
2819
#define     mod2_g2pocr5        g2pocr5_addr.bit.b2
2820
#define     prt_g2pocr5         g2pocr5_addr.bit.b3
2821
#define     ivl_g2pocr5         g2pocr5_addr.bit.b4
2822
#define     rld_g2pocr5         g2pocr5_addr.bit.b5
2823
#define     rtp_g2pocr5         g2pocr5_addr.bit.b6
2824
#define     inv_g2pocr5         g2pocr5_addr.bit.b7
2825
2826
/*------------------------------------------------------
2827
    Group 2 waveform generate control register 6
2828
------------------------------------------------------*/
2829
union byte_def g2pocr6_addr;
2830
#define     g2pocr6       g2pocr6_addr.byte
2831
2832
#define     mod0_g2pocr6        g2pocr6_addr.bit.b0
2833
#define     mod1_g2pocr6        g2pocr6_addr.bit.b1
2834
#define     mod2_g2pocr6        g2pocr6_addr.bit.b2
2835
#define     prt_g2pocr6         g2pocr6_addr.bit.b3
2836
#define     ivl_g2pocr6         g2pocr6_addr.bit.b4
2837
#define     rld_g2pocr6         g2pocr6_addr.bit.b5
2838
#define     rtp_g2pocr6         g2pocr6_addr.bit.b6
2839
#define     inv_g2pocr6         g2pocr6_addr.bit.b7
2840
2841
/*------------------------------------------------------
2842
    Group 2 waveform generate control register 7
2843
------------------------------------------------------*/
2844
union byte_def g2pocr7_addr;
2845
#define     g2pocr7       g2pocr7_addr.byte
2846
2847
#define     mod0_g2pocr7        g2pocr7_addr.bit.b0
2848
#define     mod1_g2pocr7        g2pocr7_addr.bit.b1
2849
#define     mod2_g2pocr7        g2pocr7_addr.bit.b2
2850
#define     prt_g2pocr7         g2pocr7_addr.bit.b3
2851
#define     ivl_g2pocr7         g2pocr7_addr.bit.b4
2852
#define     rld_g2pocr7         g2pocr7_addr.bit.b5
2853
#define     rtp_g2pocr7         g2pocr7_addr.bit.b6
2854
#define     inv_g2pocr7         g2pocr7_addr.bit.b7
2855
2856
/*------------------------------------------------------
2857
    Group 2 RTP output buffer register
2858
------------------------------------------------------*/
2859
union byte_def g2rtp_addr;
2860
#define     g2rtp       g2rtp_addr.byte
2861
2862
#define     rtp0_g2rtp        g2rtp_addr.bit.b0
2863
#define     rtp1_g2rtp        g2rtp_addr.bit.b1
2864
#define     rtp2_g2rtp        g2rtp_addr.bit.b2
2865
#define     rtp3_g2rtp        g2rtp_addr.bit.b3
2866
#define     rtp4_g2rtp        g2rtp_addr.bit.b4
2867
#define     rtp5_g2rtp        g2rtp_addr.bit.b5
2868
#define     rtp6_g2rtp        g2rtp_addr.bit.b6
2869
#define     rtp7_g2rtp        g2rtp_addr.bit.b7
2870
2871
/*------------------------------------------------------
2872
    Group 2 function enable register
2873
------------------------------------------------------*/
2874
union byte_def g2fe_addr;
2875
#define     g2fe       g2fe_addr.byte
2876
2877
#define     ife0_g2fe        g2fe_addr.bit.b0
2878
#define     ife1_g2fe        g2fe_addr.bit.b1
2879
#define     ife2_g2fe        g2fe_addr.bit.b2
2880
#define     ife3_g2fe        g2fe_addr.bit.b3
2881
#define     ife4_g2fe        g2fe_addr.bit.b4
2882
#define     ife5_g2fe        g2fe_addr.bit.b5
2883
#define     ife6_g2fe        g2fe_addr.bit.b6
2884
#define     ife7_g2fe        g2fe_addr.bit.b7
2885
2886
/*------------------------------------------------------
2887
    Group 2 SI/O communication mode register
2888
------------------------------------------------------*/
2889
union byte_def g2mr_addr;
2890
#define     g2mr       g2mr_addr.byte
2891
2892
#define     gmd0_g2mr         g2mr_addr.bit.b0
2893
#define     gmd1_g2mr         g2mr_addr.bit.b1
2894
#define     ckdir_g2mr        g2mr_addr.bit.b2
2895
#define     uform_g2mr        g2mr_addr.bit.b6
2896
#define     irs_g2mr          g2mr_addr.bit.b7
2897
2898
/*------------------------------------------------------
2899
    Group 2 SI/O communication control register
2900
------------------------------------------------------*/
2901
union byte_def g2cr_addr;
2902
#define     g2cr       g2cr_addr.byte
2903
2904
#define     te_g2cr             g2cr_addr.bit.b0
2905
#define     txept_g2cr          g2cr_addr.bit.b1
2906
#define     ti_g2cr             g2cr_addr.bit.b2
2907
#define     re_g2cr             g2cr_addr.bit.b4
2908
#define     ri_g2cr             g2cr_addr.bit.b5
2909
#define     opol_g2cr           g2cr_addr.bit.b6
2910
#define     ipol_g2cr           g2cr_addr.bit.b7
2911
2912
/*------------------------------------------------------
2913
    Group 2 IEBus control register
2914
------------------------------------------------------*/
2915
union byte_def iecr_addr;
2916
#define     iecr       iecr_addr.byte
2917
2918
#define     ieb            iecr_addr.bit.b0
2919
#define     iets           iecr_addr.bit.b1
2920
#define     iebbs          iecr_addr.bit.b2
2921
#define     df             iecr_addr.bit.b6
2922
#define     iem            iecr_addr.bit.b7
2923
2924
/*------------------------------------------------------
2925
    Group 2 IEBus receive interrupt cause detect register
2926
------------------------------------------------------*/
2927
union byte_def ierif_addr;
2928
#define     ierif       ierif_addr.byte
2929
2930
#define     iernf          ierif_addr.bit.b0
2931
#define     iepar          ierif_addr.bit.b1
2932
#define     iermb          ierif_addr.bit.b2
2933
#define     iert           ierif_addr.bit.b3
2934
#define     ieretc         ierif_addr.bit.b4
2935
2936
/*------------------------------------------------------
2937
    Group 2 IEBus receive interrupt cause detect register
2938
------------------------------------------------------*/
2939
union byte_def ietif_addr;
2940
#define     ietif       ietif_addr.byte
2941
2942
#define     ietnf          ietif_addr.bit.b0
2943
#define     ieack          ietif_addr.bit.b1
2944
#define     ietmb          ietif_addr.bit.b2
2945
#define     iett           ietif_addr.bit.b3
2946
#define     ieabl          ietif_addr.bit.b4
2947
2948
/*------------------------------------------------------
2949
    Group 3 base timer control register 0
2950
------------------------------------------------------*/
2951
union byte_def g3bcr0_addr;
2952
#define     g3bcr0       g3bcr0_addr.byte
2953
2954
#define     bck0_g3bcr0        g3bcr0_addr.bit.b0
2955
#define     bck1_g3bcr0        g3bcr0_addr.bit.b1
2956
#define     div0_g3bcr0        g3bcr0_addr.bit.b2
2957
#define     div1_g3bcr0        g3bcr0_addr.bit.b3
2958
#define     div2_g3bcr0        g3bcr0_addr.bit.b4
2959
#define     div3_g3bcr0        g3bcr0_addr.bit.b5
2960
#define     div4_g3bcr0        g3bcr0_addr.bit.b6
2961
#define     it_g3bcr0          g3bcr0_addr.bit.b7
2962
2963
/*------------------------------------------------------
2964
    Group 3 base timer control register 1
2965
------------------------------------------------------*/
2966
union byte_def g3bcr1_addr;
2967
#define     g3bcr1       g3bcr1_addr.byte
2968
2969
#define     rst0_g3bcr1        g3bcr1_addr.bit.b0
2970
#define     rst1_g3bcr1        g3bcr1_addr.bit.b1
2971
#define     rst2_g3bcr1        g3bcr1_addr.bit.b2
2972
//#define                rst3_g3bcr1                   g3bcr1_addr.bit.b3
2973
#define     bts_g3bcr1         g3bcr1_addr.bit.b4
2974
//#define                ud0_g3bcr1                   g3bcr1_addr.bit.b5
2975
//#define                ud1_g3bcr1                   g3bcr1_addr.bit.b6
2976
#define     prp_g3bcr1         g3bcr1_addr.bit.b7
2977
2978
/*------------------------------------------------------
2979
    Group 3 waveform generate control register 0
2980
------------------------------------------------------*/
2981
union byte_def g3pocr0_addr;
2982
#define     g3pocr0       g3pocr0_addr.byte
2983
2984
#define     mod0_g3pocr0        g3pocr0_addr.bit.b0
2985
#define     mod1_g3pocr0        g3pocr0_addr.bit.b1
2986
#define     mod2_g3pocr0        g3pocr0_addr.bit.b2
2987
#define     prt_g3pocr0         g3pocr0_addr.bit.b3
2988
#define     ivl_g3pocr0         g3pocr0_addr.bit.b4
2989
#define     rld_g3pocr0         g3pocr0_addr.bit.b5
2990
#define     rtp_g3pocr0         g3pocr0_addr.bit.b6
2991
#define     inv_g3pocr0         g3pocr0_addr.bit.b7
2992
2993
2994
/*------------------------------------------------------
2995
    Group 3 waveform generate control register 1
2996
------------------------------------------------------*/
2997
union byte_def g3pocr1_addr;
2998
#define     g3pocr1       g3pocr1_addr.byte
2999
3000
#define     mod0_g3pocr1        g3pocr1_addr.bit.b0
3001
#define     mod1_g3pocr1        g3pocr1_addr.bit.b1
3002
#define     mod2_g3pocr1        g3pocr1_addr.bit.b2
3003
#define     prt_g3pocr1         g3pocr1_addr.bit.b3
3004
#define     ivl_g3pocr1         g3pocr1_addr.bit.b4
3005
#define     rld_g3pocr1         g3pocr1_addr.bit.b5
3006
#define     rtp_g3pocr1         g3pocr1_addr.bit.b6
3007
#define     inv_g3pocr1         g3pocr1_addr.bit.b7
3008
3009
/*------------------------------------------------------
3010
    Group 3 waveform generate control register 2
3011
------------------------------------------------------*/
3012
union byte_def g3pocr2_addr;
3013
#define     g3pocr2       g3pocr2_addr.byte
3014
3015
#define     mod0_g3pocr2        g3pocr2_addr.bit.b0
3016
#define     mod1_g3pocr2        g3pocr2_addr.bit.b1
3017
#define     mod2_g3pocr2        g3pocr2_addr.bit.b2
3018
#define     prt_g3pocr2         g3pocr2_addr.bit.b3
3019
#define     ivl_g3pocr2         g3pocr2_addr.bit.b4
3020
#define     rld_g3pocr2         g3pocr2_addr.bit.b5
3021
#define     rtp_g3pocr2         g3pocr2_addr.bit.b6
3022
#define     inv_g3pocr2         g3pocr2_addr.bit.b7
3023
3024
/*------------------------------------------------------
3025
    Group 3 waveform generate control register 3
3026
------------------------------------------------------*/
3027
union byte_def g3pocr3_addr;
3028
#define     g3pocr3       g3pocr3_addr.byte
3029
3030
#define     mod0_g3pocr3        g3pocr3_addr.bit.b0
3031
#define     mod1_g3pocr3        g3pocr3_addr.bit.b1
3032
#define     mod2_g3pocr3        g3pocr3_addr.bit.b2
3033
#define     prt_g3pocr3         g3pocr3_addr.bit.b3
3034
#define     ivl_g3pocr3         g3pocr3_addr.bit.b4
3035
#define     rld_g3pocr3         g3pocr3_addr.bit.b5
3036
#define     rtp_g3pocr3         g3pocr3_addr.bit.b6
3037
#define     inv_g3pocr3         g3pocr3_addr.bit.b7
3038
3039
/*------------------------------------------------------
3040
    Group 3 waveform generate control register 4
3041
------------------------------------------------------*/
3042
union byte_def g3pocr4_addr;
3043
#define     g3pocr4       g3pocr4_addr.byte
3044
3045
#define     mod0_g3pocr4        g3pocr4_addr.bit.b0
3046
#define     mod1_g3pocr4        g3pocr4_addr.bit.b1
3047
#define     mod2_g3pocr4        g3pocr4_addr.bit.b2
3048
#define     prt_g3pocr4         g3pocr4_addr.bit.b3
3049
#define     ivl_g3pocr4         g3pocr4_addr.bit.b4
3050
#define     rld_g3pocr4         g3pocr4_addr.bit.b5
3051
#define     rtp_g3pocr4         g3pocr4_addr.bit.b6
3052
#define     inv_g3pocr4         g3pocr4_addr.bit.b7
3053
3054
/*------------------------------------------------------
3055
    Group 3 waveform generate control register 5
3056
------------------------------------------------------*/
3057
union byte_def g3pocr5_addr;
3058
#define     g3pocr5       g3pocr5_addr.byte
3059
3060
#define     mod0_g3pocr5        g3pocr5_addr.bit.b0
3061
#define     mod1_g3pocr5        g3pocr5_addr.bit.b1
3062
#define     mod2_g3pocr5        g3pocr5_addr.bit.b2
3063
#define     prt_g3pocr5         g3pocr5_addr.bit.b3
3064
#define     ivl_g3pocr5         g3pocr5_addr.bit.b4
3065
#define     rld_g3pocr5         g3pocr5_addr.bit.b5
3066
#define     rtp_g3pocr5         g3pocr5_addr.bit.b6
3067
#define     inv_g3pocr5         g3pocr5_addr.bit.b7
3068
3069
/*------------------------------------------------------
3070
    Group 3 waveform generate control register 6
3071
------------------------------------------------------*/
3072
union byte_def g3pocr6_addr;
3073
#define     g3pocr6       g3pocr6_addr.byte
3074
3075
#define     mod0_g3pocr6        g3pocr6_addr.bit.b0
3076
#define     mod1_g3pocr6        g3pocr6_addr.bit.b1
3077
#define     mod2_g3pocr6        g3pocr6_addr.bit.b2
3078
#define     prt_g3pocr6         g3pocr6_addr.bit.b3
3079
#define     ivl_g3pocr6         g3pocr6_addr.bit.b4
3080
#define     rld_g3pocr6         g3pocr6_addr.bit.b5
3081
#define     rtp_g3pocr6         g3pocr6_addr.bit.b6
3082
#define     inv_g3pocr6         g3pocr6_addr.bit.b7
3083
3084
/*------------------------------------------------------
3085
    Group 3 waveform generate control register 7
3086
------------------------------------------------------*/
3087
union byte_def g3pocr7_addr;
3088
#define     g3pocr7       g3pocr7_addr.byte
3089
3090
#define     mod0_g3pocr7        g3pocr7_addr.bit.b0
3091
#define     mod1_g3pocr7        g3pocr7_addr.bit.b1
3092
#define     mod2_g3pocr7        g3pocr7_addr.bit.b2
3093
#define     prt_g3pocr7         g3pocr7_addr.bit.b3
3094
#define     ivl_g3pocr7         g3pocr7_addr.bit.b4
3095
#define     rld_g3pocr7         g3pocr7_addr.bit.b5
3096
#define     rtp_g3pocr7         g3pocr7_addr.bit.b6
3097
#define     inv_g3pocr7         g3pocr7_addr.bit.b7
3098
3099
/*------------------------------------------------------
3100
    Group 3 RTP output buffer register
3101
------------------------------------------------------*/
3102
union byte_def g3rtp_addr;
3103
#define     g3rtp       g3rtp_addr.byte
3104
3105
#define     rtp0_g3rtp        g3rtp_addr.bit.b0
3106
#define     rtp1_g3rtp        g3rtp_addr.bit.b1
3107
#define     rtp2_g3rtp        g3rtp_addr.bit.b2
3108
#define     rtp3_g3rtp        g3rtp_addr.bit.b3
3109
#define     rtp4_g3rtp        g3rtp_addr.bit.b4
3110