Revision 2

View differences:

trunk/tp_info6/Emb_App.tws
7 7
[GENERAL_DATA]
8 8
[BREAKPOINTS]
9 9
[OPEN_WORKSPACE_FILES]
10
"E:\tp_info6\tp_info6_etud\Emb_App\crt0mr.a30" 
11
"E:\tp_info6\tp_info6_etud\Emb_App\programme_principal_etud.c" 
10
"E:\tp_info6\tp_info6\Emb_App\crt0mr.a30" 
11
"E:\tp_info6\tp_info6\Emb_App\programme_principal_etud.c" 
12 12
[WORKSPACE_FILE_STATES]
13
"E:\tp_info6\tp_info6_etud\Emb_App\crt0mr.a30" 0 0 1426 347 0 0 
14
"E:\tp_info6\tp_info6_etud\Emb_App\programme_principal_etud.c" -8 -30 1596 539 1 1 
13
"E:\tp_info6\tp_info6\Emb_App\crt0mr.a30" -8 -30 1596 539 1 0 
14
"E:\tp_info6\tp_info6\Emb_App\programme_principal_etud.c" 25 25 1426 347 0 1 
15 15
[LOADED_PROJECTS]
16 16
"EmbM32C87App" 
17 17
[END]
trunk/tp_info6/Emb_App/radiocommande.c
1
/***********************************************************************/
2
/*                                                                     */
3
/*  FILE        :radiocommande.c                                       */
4
/*  DATE        :Mon, Feb 13, 2006                                     */
5
/*  DESCRIPTION : measure 6 channels on the receiver                   */
6
/*  CPU GROUP   :62P                                                   */
7
/*                                                                     */
8
/*  This file is generated by Renesas Project Generator (Ver.4.5).     */
9
/*                                                                     */
10
/***********************************************************************/
11
#ifdef M32C87
12
	#include "sfr32c87.h"
13
#endif
14

  
15
#ifdef M32C83
16
	#include "sfr32c83.h"
17
#endif
18

  
19
#include <itron.h> 
20
#include <kernel.h> 
21
#include "kernel_id.h" 
22

  
23

  
24
//function's prototypes declaration
25

  
26

  
27

  
28
int canal[7];
29
int canal_ok;
30

  
31

  
32
void capture_init(void)
33
{
34
     prc2 = 1;                //unprotect writing in pd9 register
35
     pd9_0 = 0;
36
	 prc2=0;
37
	 ps3_3=0;
38
	 psl3_3=0;
39
     tb0mr = 0x4A;            //timer B0 in duration measurement mode with f8
40
     tb0ic = 0x07;            //enable timer B0 interrupt at level x
41
     tb0s = 1;                //start timer B0
42
	 
43
	 canal_ok=0;
44
}
45

  
46
void mesure(void)
47
{
48
     static char k=-1;
49
	 static int flag=0;
50
	 unsigned int tpulse;
51
	 int val; 
52
	
53
	tpulse=tb0>>1; // Pulse time 
54

  
55
	if (tpulse<400) { // Too short pulse
56
		k=-1;
57
		canal_ok=0;
58
		return;
59
	}	
60
	
61
	if (tpulse>10000) // Synchro pulse
62
	{
63
		k=0; // Return to canal 0
64
		return;
65
	}
66
	
67
	if (k==(char) -1) // Not synchronised
68
		return; // Nothing to do
69

  
70
	if (!(k & 0x01))  // 500us High pulse
71
		if (tpulse>600) {
72
			k=-1; // Invalidate mesure and wait a new synchro
73
			canal_ok=0;
74
			return;
75
		}
76

  
77
	if (k & 0x01) // Pulse timing
78
		canal[k>>1]=tpulse-1360; // 1360 neutral zone
79

  
80
	k++;
81
	if (k>11) {// Last canal
82
		k=-1;
83
		canal_ok=1;
84
	}
85
}
trunk/tp_info6/Emb_App/radiocommande.h
1
void mesure(void);
2
void init_capture(void);
trunk/tp_info6/Emb_App/dma0.c
1
// subroutines for control DMA0
2

  
3
#ifdef M32C87
4
	#include "sfr32c87.h"
5
#endif
6

  
7
#ifdef M32C83
8
	#include "sfr32c83.h"
9
#endif
10

  
11
#include <itron.h> 
12
#include <kernel.h> 
13
#include "kernel_id.h" 
14
#include "dma0.h"
15

  
16
unsigned char dma0_fin_tr;
17

  
18
void dma0_init(void)
19
{
20
    dmd0 = 0x00;            //invalide canaux 0&1 DMA
21
	dm0ic = 0x05;			// valide interruption dma canal 0
22
    dm0sl = 0x8E;           // transfert sur interruption emission uart0
23
    dsa0 = &u0tb;           // adresse destination
24
    asm (" nop ");
25
    asm (" nop ");
26
    asm (" nop ");
27
    asm (" nop ");
28
    asm (" nop ");
29
    asm (" nop ");
30
    //dmd0 = 0x09;            // canal 0 actif en mode monocoup avec mot code sur 8 bits	
31
}
32

  
33
/*
34

  
35
// declaration variable
36

  
37
void initdma0(void)
38
{
39
    dmd0 = 0x00;            //invalide canaux 0&1 DMA
40
    dm0sl = 0x8E;           // transfert sur interruption emission uart0
41
//    dma0 = &buf_em[1];      // adresse source
42
    dsa0 = &u0tb;           // adresse destination
43
    dct0 = 0x00;            // taille buffer - 1
44
    asm (" nop ");
45
    asm (" nop ");
46
    asm (" nop ");
47
    asm (" nop ");
48
    asm (" nop ");
49
    asm (" nop ");
50
    dmd0 = 0x09;            // canal 0 actif en mode monocoup avec mot code sur 8 bits
51
}            
52
*/
53

  
54
void uart0_dma0_tr_OK(void)
55
{
56
	s0tic=3; // Autorise les interruptions Uart pour detecter la fin de l'envoi du dernier caractere
57
	//s0tic&=~0x08; // Effacer la demande d'int uart0
58
	// Pour eviter un risque de prise en compte anticip?
59
	// Les interruption DMA0 et 
60
	dma0_fin_tr=1;
61
	//iset_flg(ev_bus_fin_tr,(UINT) 1);
62
}
63

  
64
void uart0_str_dma0 (char str[])
65
{
66
	dmd0 = 0x00;                                // initialise nouveau transfert
67
	dct0 = strlen(str)-1;
68
	dma0 = &str[1];
69
	dm0sl = 0x8e;
70
	dsa0 = &u0tb;           // adresse destination
71
    asm (" nop ");
72
    asm (" nop ");
73
    asm (" nop ");
74
    asm (" nop ");
75
    asm (" nop ");
76
    asm (" nop ");
77
	dmd0 = 0x09;
78
	s0tic=0; 		// Arret par securit? des int uart0 tx
79
	dm0ic=7;	
80
	dma0_fin_tr=0; // Utile pour eviter des collision de message lors de la prise 
81
				   // du processeur par le debugger			   
82
	u0tb = str[0];   
83
}
84

  
85
void uart0_dma0_itx()
86
{
87
	if (dma0_fin_tr){
88
		iset_flg(ev_bus_fin_tr,(UINT) 1);
89
		dma0_fin_tr=0;
90
	}
91
	s0tic=0; // Interruption bloqu?s jusqu'a la fin d'un transfert dma
92
}
trunk/tp_info6/Emb_App/mli.c
1
// fonction de gestion MLI
2
#include "sfr32c87.h"
3

  
4
void mli_init(void)
5
{
6
	tb2mr = 0x40;			// TB2 en mode timer avec horloge f8
7
	tb2 = 24999;			// periode de 10 ms	
8
	ta1mr = 0x52;			// TA1 en mode monocoup avec horloge f8 et declenchement par debordement de TB2
9
	ta1 = 3249;				// reglage temps etat haut de 1300 ns
10
	ta2mr = 0x52;			// TA2 en mode monocoup avec horloge f8 et declenchement par debordement de TB2
11
	ta2 = 3249;				// reglage temps etat haut de 1300 ns
12
	trgsr = 0x05;
13
	ta1ic = 0x00;			// RAZ drapeau et aucune interruption
14
	ta2ic = 0;
15
	tb2ic = 0;
16
	psl1_2 = 1;				// configure P72/TA1OUT en sortie timer A1
17
	ps1_2 = 1;
18
	psc_4 = 0;				// configure P74/TA2OUT en sortie timer A2
19
	psl1_4 = 0;
20
	ps1_4 = 1;
21
//	tabsr = 0x86;			// demarre timer B2, A2 et A1
22
	tb2s=1;
23
	ta1s=1;
24
	ta2s=1;
25
}
26

  
27
void mli_voie_1(unsigned short rc)
28
{
29
	if (rc > 4999) rc = 4999;	// bornage rapport cyclique maxi
30
	if (rc < 1999) rc = 1999;	// bornage rapport cyclique mini
31
	ta1 = rc;	
32
}
33

  
34
void mli_voie_2(unsigned short rc)
35
{
36
	if (rc > 4999) rc = 4999;	// bornage rapport cyclique maxi
37
	if (rc < 1999) rc = 1999;	// bornage rapport cyclique mini
38
	ta2 = rc;
39
}		
trunk/tp_info6/Emb_App/clavier.c
1
// subroutines for control the matriced keyboard
2

  
3
#ifdef M32C87
4
	#include "sfr32c87.h"
5
#endif
6

  
7
#ifdef M32C83
8
	#include "sfr32c83.h"
9
#endif
10

  
11
#include <itron.h> 
12
#include <kernel.h> 
13
#include <kernel_api.h>
14
#include "kernel_id.h" 
15

  
16
#ifdef M32C87
17
void clavier_init(int int_level)
18
{
19
     pd10= 0x0F;              // bit7 to bit4 input      bit3 to bit0 output   for port 10
20
	 p10= 0xF0;
21
     pu31 = 1;                 // pull up enable for pins P10_7 to P10_4
22
     kupic = int_level;        // set key interrupt level
23
}
24

  
25
unsigned char clavier_scan(void)
26
{
27
	unsigned char touche; 
28
	static unsigned char ltouche;
29
	const unsigned char t_scan[4]={~(1<<0),~(1<<1),~(1<<2),~(1<<3)};
30
	static int col=0;
31
		
32
		p10=t_scan[col++];
33
		col&=0x03;
34
			
35
    	touche = p10;			// lecture code binaire clavier
36
		switch(touche)					//determine et affiche numero touche appuyee
37
     	   {
38
     	   	case 0xBE: 
39
				 touche = '1';
40
     	   	     break;
41
     	   	case 0xDE: 
42
     	   	     touche = '2';
43
     	   	     break;
44
     	   	case 0x7E: 
45
     	   	     touche = '3';
46
                 break;
47
            case 0xBD: 
48
                 touche = '4';
49
                 break;
50
            case 0xDD: 
51
                 touche = '5';
52
     	   	     break;
53
     	   	case 0x7D: 
54
     	   	     touche = '6';
55
                 break;
56
            case 0xEB: 
57
     	   	     touche = '7';
58
                 break;
59
     	   	case 0xDB: 
60
     	   	     touche = '8';
61
     	   	     break;
62
     	   	case 0x7B: 
63
     	   	     touche = '9';
64
                 break;
65
            case 0xE7: 
66
                 touche = '*';
67
     	   	     break;
68
     	   	case 0xD7: 
69
     	   	     touche = '0';
70
     	   	     break;
71
     	   	case 0x77: 
72
     	   	     touche = '#';
73
                 break;
74
            default : touche = 0;
75
                 break;
76
		   }	 
77
		return( touche );		 
78
}
79

  
80
int touche_filter(void)
81
{
82
SYSTIM time;
83
static SYSTIM ltime;
84
SYSTIM dtime;
85

  
86
	iget_tim(&time);
87
	
88
	dtime.utime=time.utime-ltime.utime;	
89
	
90
	if (time.ltime<ltime.ltime)
91
		dtime.utime--;
92
		
93
	dtime.ltime=time.ltime-ltime.ltime;
94
	
95
	ltime.utime=time.utime;
96
	ltime.ltime=time.ltime;
97
		
98
	if (dtime.utime>0)
99
		return 1;
100
	else if (dtime.ltime>100)
101
		return 1;
102
		
103
	return 0;
104
}
105

  
106
void itouche(void )
107
{
108
	char t;
109
	
110
	if (t=clavier_scan()){ 
111
		if (touche_filter())
112
			vipsnd_dtq(QdmTouche,t);
113
	}
114
	p10=0xF0;			
115
}
116

  
117
#endif
118

  
119
#ifdef M32C83
120

  
121
// Clavier M32C83 Carte Lp
122

  
123
void clavier_init(int level)
124
{
125
    pd4 &= 0x0F;        //p44->P47 inputs   p40 -> p44 outputs
126
    pd5 = 0xFF;         //port 5 outputs
127
    p5 = 0xFD;
128
}
129

  
130

  
131

  
132
unsigned char clavier_scan(void)
133
{
134
    unsigned int code;
135
    unsigned int row;
136
    unsigned int colum;
137
    static unsigned char table[] = {0x7F,0xBF,0xEF,0xF7,0xFB,0xFD};
138
	static int i=0;
139

  
140
    p5 = colum = table[i];    
141
    i++;
142
    if(i==6) i=0;
143

  
144
    row = p4 & 0xF0;
145
    code = (colum << 8) | row;
146

  
147
    switch(code)
148
    {
149
        case(0x7F70) : return('/');
150
                    break;
151
        case(0xBF70) : return('*');
152
                    break;
153
        case(0xEF70) : return('F');
154
                    break;
155
        case(0xF770) : return('E');
156
                    break;
157
        case(0xFB70) : return('D');
158
                    break;
159
        case(0xFD70) : return('C');
160
                    break;
161
        case(0x7FB0) : return('X');
162
                    break;
163
        case(0xBFB0) : return('#');
164
                    break;
165
        case(0xEFB0) : return('B');
166
                    break;
167
        case(0xF7B0) : return('A');
168
                    break;
169
        case(0xFBB0) : return('9');
170
                    break;
171
        case(0xFDB0) : return('8');
172
                    break;
173
        case(0x7FD0) : return('-');
174
                    break;
175
        case(0xBFD0) : return('.');
176
                    break;
177
        case(0xEFD0) : return('7');
178
                    break;
179
        case(0xF7D0) : return('6');
180
                    break;
181
        case(0xFBD0) : return('5');
182
                    break;
183
        case(0xFDD0) : return('4');
184
                    break;
185
        case(0x7FE0) : return('+');
186
                    break;
187
        case(0xBFE0) : return('=');
188
                    break;
189
        case(0xEFE0) : return('3');
190
                    break;
191
        case(0xF7E0) : return('2');
192
                    break;
193
        case(0xFBE0) : return('1');
194
                    break;
195
        case(0xFDE0) : return('0');
196
                    break;
197
        default : return(0);  // Si aucune touche renvoi 0 plus facile a tester
198
                    break;
199
    }
200
}
201

  
202
void itouche(void) // Dummy fonction compatibility with Polytech Card
203
{}
204

  
205
#endif
trunk/tp_info6/Emb_App/dma0.h
1
// Header for DMA0 control
2

  
3
// declaration registre interne CPU
4
unsigned short dmd0;
5
#pragma DMAC dmd0 DMD0      // DMA mode register channel 0 and 1
6
unsigned short dct0;
7
#pragma DMAC dct0 DCT0      // DMA transfert count regsiter channel 0
8
unsigned short drc0;
9
#pragma DMAC drc0 DRC0      // DMA transfert count reload register channel 0
10
void _far *dma0;
11
#pragma DMAC dma0 DMA0      // DMA memory address register channel 0
12
void _far *dsa0;
13
#pragma DMAC dsa0 DSA0      // DMA sfr address register channel 0
14
void _far *dra0;
15
#pragma DMAC dra0 DRA0      // DMA memory address reload register channel 0
16

  
17
unsigned short dct1;
18
#pragma DMAC dct1 DCT1      // DMA transfert count regsiter channel 1
19
unsigned short drc1;
20
#pragma DMAC drc1 DRC1      // DMA transfert count reload register channel 1
21
void _far *dma1;
22
#pragma DMAC dma1 DMA1      // DMA memory address register channel 1
23
void _far *dsa1;
24
#pragma DMAC dsa1 DSA1      // DMA sfr address register channel 1
25
void _far *dra1;
26
#pragma DMAC dra1 DRA1      // DMA memory address reload register channel 1
27

  
28
// declaration prototype fonctions
29
void dma0_init(void);
30
void uart0_str_dma0 (char str[]);
31
void uart0_dma0_itx();
trunk/tp_info6/Emb_App/mli.h
1
// prototypes des fonctions de gestion des MLI
2

  
3
void mli_init(void);
4
void mli_voie_1(unsigned short rc);
5
void mli_voie_2(unsigned short rc);
trunk/tp_info6/Emb_App/periph.c
1
#ifdef M32C87
2
	#include "sfr32c87.h"
3
#endif
4

  
5
#ifdef M32C83
6
	#include "sfr32c83.h"
7
#endif
8

  
9

  
10
#include <itron.h> 
11
#include <kernel.h> 
12
#include "kernel_id.h" 
13
#include "periph.h"
14
#include "uart0.h"
15
#include "dma0.h";
16

  
17

  
18

  
19
Tperiph periph[26];
20

  
21
#define eot 0x0D
22

  
23
void periph_init (void)
24
{
25
int i;
26
	uart0_init();
27
    dma0_init();
28
	for (i=0;i<26;i++)
29
		periph[i].maj=periph[i].val=periph[i].ev=0;
30
		
31
}
32

  
33
void periph_nom(char * nom){
34
char c;
35
int i=0;
36
	c=*nom;
37
	do{
38
		periph_write('I',c);
39
		dly_tsk(0);
40
		i++;
41
		if (i>=8) break;
42
	}while (c=*(++nom));
43
	periph_write('I',0);
44
	dly_tsk(0);
45
}
46

  
47
int periph_read (unsigned char a,int * val)
48
{
49
int i;
50
/*	addr &= ~0x20;
51
	addr = addr -'A';
52
	if (addr>26)
53
		return 0;
54
*/	
55
	if (!periph[ADDR(a)].maj){
56
		periph_inter(a);
57
	//	dly_tsk(10);
58
	}
59
	if (periph[ADDR(a)].maj) {
60
		periph[ADDR(a)].maj=0;
61
		*val = periph[ADDR(a)].val;
62
		return 1;
63
	}
64
	*val = periph[ADDR(a)].val;
65
	return 0;
66
}
67

  
68
void periph_write(char addr,int valeur)
69
{
70
CanFrame comm; 
71
	comm.data.id=addr; comm.data.rtr=':'; comm.data.val=valeur;
72
	snd_dtq (CanTx, (VP_INT) comm.msg);
73
}
74

  
75
void iperiph_write(char addr,int valeur)
76
{
77
CanFrame comm; 
78
	comm.data.id=addr; comm.data.rtr=':'; comm.data.val=valeur;
79
	ipsnd_dtq (CanTx, (VP_INT) comm.msg);
80
}
81

  
82
void periph_inter(char addr)
83
{
84
CanFrame comm;
85
	comm.data.id=addr; comm.data.rtr='?';
86
	snd_dtq (CanTx,(VP_INT) comm.msg);
87
}
88

  
89
void iperiph_inter(char addr)
90
{
91
CanFrame comm;
92
	comm.data.id=addr; comm.data.rtr='?';
93
	ipsnd_dtq (CanTx,(VP_INT) comm.msg);
94
}
95

  
96
void periph_even(char addr)
97
{
98
CanFrame comm;
99
	comm.data.id=addr; comm.data.rtr='!';
100
	snd_dtq (CanTx,(VP_INT) comm.msg);	
101
}
102

  
103
void iperiph_even(char addr)
104
{
105
CanFrame comm;
106
	comm.data.id=addr; comm.data.rtr='!';
107
	ipsnd_dtq (CanTx,(VP_INT) comm.msg);	
108
}
109

  
110
static int hex_2_int (char * str)
111
{
112
	int i;
113
	long val;
114
	val=0;
115
	for (i=0;i<4;i++)
116
	{
117
		val=(val*16);
118
		val+=(str[i]>='A')?(int) str[i]-'A'+10:(int)str[i]-'0';
119
	}
120
	if (val>0x7FFF) val=val-0x10000;
121
	return val;
122
}
123

  
124
static void int_2_hex(unsigned int val, char * str)
125
{
126
	int i;
127
	char c;
128
	
129
	for (i=3;i>=0;i--)
130
	{
131
		c = val & 0x0F;
132
		c+='0';
133
		if (c>'9') c+='A'-'9'-1;
134
		str[i]=c;
135
		val=val>>4;
136
	}
137
}
138

  
139
void periph_rx(VP_INT foo)
140
{
141
char c;
142
unsigned int valeur;
143
CanFrame msg;
144

  
145
	while (1)
146
	{
147
		if (rcv_dtq (CanRx,(VP_INT *) &msg)==E_OK)
148
		{
149
			c=msg.data.id;
150
			if (c=='!'){
151
				set_flg(event,msg.data.val);
152
				continue;
153
			}
154
			if (c<'A' || c>'z')
155
				continue;	
156
			c=ADDR(msg.data.id);
157
		
158
			if (msg.data.rtr=='!'){
159
				periph[c].val=1;
160
				periph[c].maj++;
161
				if (periph[c].ev)
162
					set_flg(ev_periph,periph[c].ev);
163
				continue;
164
			}
165

  
166
			if (msg.data.rtr==':'){
167
				periph[c].val=msg.data.val;
168
				periph[c].maj++;
169
				if (periph[c].ev)
170
					set_flg(ev_periph,periph[c].ev);				
171
				continue;
172
			}
173
		}
174
	}
175
}
176

  
177
void periph_tx(VP_INT foo)                                     // test emission trame formatee
178
{
179
CanFrame rec;
180
char buf_em[8];
181
UINT flag;
182
char valid;
183

  
184
	while(1)
185
	{
186
  		if (rcv_dtq (CanTx,(VP_INT *) &rec.msg)==E_OK)
187
        {
188
			//buf_em[0]=eot; //0x0A??
189
			buf_em[0]=rec.data.id;
190
			valid=0;
191
			if (rec.data.rtr==':' || rec.data.rtr==0){
192
				buf_em[1]=':';
193
				int_2_hex (rec.data.val,&buf_em[2]);
194
				buf_em[6]=eot; 
195
				buf_em[7]=0;
196
				valid=1;
197
			}
198
			if (rec.data.rtr=='?' || rec.data.rtr==1){
199
				buf_em[1]='?';
200
				buf_em[2]=eot;
201
				buf_em[3]=0;
202
				//buf_em[3]=buf_em[4]=buf_em[5]=buf_em[6]='-';
203
				//buf_em[4]=0;
204
				valid=1;
205
			}	
206
			if (!valid)
207
				continue;	
208
						
209
			uart0_itx(buf_em);						
210
/*			uart0_str_dma(buf_em);   // declenche transfert
211
			// Attention le debugger peu prendre la main n'importe quand et bloquer
212
			// la detection de fin d'envoi de message
213
			// Le timeout permet de debloquer la situation 
214

  
215
			wai_flg(ev_bus_fin_tr,(FLGPTN) 0x0001,TWF_ANDW,&flag);
216

  
217
			//twai_flg(ev_bus_fin_tr,(FLGPTN) 0x0001,TWF_ANDW,&flag,5);
218
			//clr_flg( ID_ev_bus_fin_tr,(FLGPTN) 0); 
219
*/			
220
			wai_flg(ev_bus_fin_tr,(FLGPTN) 0x0001,TWF_ANDW,&flag);
221
        }                                            
222
	}
223
}
224

  
225

  
trunk/tp_info6/Emb_App/clavier.h
1
// Header file of matriced keyboard
2

  
3
void clavier_init(int int_level);
4
unsigned char clavier_scan();
trunk/tp_info6/Emb_App/uart0.c
1
// subroutines for control uart0 in interrupt mode for sending and receiving
2

  
3
#ifdef M32C87
4
	#include "sfr32c87.h"
5
#endif
6

  
7
#ifdef M32C83
8
	#include "sfr32c83.h"
9
#endif
10

  
11
#include <string.h>
12
#include <itron.h> 
13
#include <kernel.h> 
14
#include "kernel_id.h" 
15
#include "dma0.h"
16
#include "uart0.h"
17
#include "periph.h"
18

  
19
#define rx_buff_len 8
20
char rx_buff[rx_buff_len];
21
extern unsigned char dma0_fin_tr;
22

  
23
void uart0_init(void)
24
{
25
     u0mr = 0x05;              // transfert 8 bits 1 bit de stop sans parite
26
     u0c0 = 0x10;              // f1 selectionnee pas de CTS/RTS
27
     u0c1 = 0x05;              // emission et reception validees
28
								// Fbaud = Fquartz / 16  /(n+1)
29
								// n=(20 000 000 / Fbaud /16)-1
30
#ifdef M32C83								
31
// Carte M32C83 Lp							
32
     u0brg = 32000000/16/115200;     
33
#endif
34
#ifdef M32C87
35
// Carte M32C87 Cust           
36
	 u0brg = 20000000/16/115200;
37
#endif
38

  
39
     s0tic = 0x00;             // aucune interruption en emission drapeau=0
40
     pd6_2 =0;              // broche RXD0 (P62) en entr?e
41
     pd6_3 =1;              // broche TXD0 (P63) en sortie
42
     ps0_2 =0;              // ps0_2 = 0
43
     ps0_3 =1;              // ps0_3 = 1
44
	 s0ric = 0x04;
45
}
46

  
47
char uart0_tx(char c)
48
{
49
     	while(!ti_u0c1);  //wait for free transmit register
50
     	return u0tbl = c;       //send character
51
}
52

  
53

  
54

  
55
void uart0_str(char str[])
56
{
57
	while (uart0_tx(*str++));
58
}
59

  
60
void uart0_irx()
61
{
62
static int n=0;
63
char c;
64
static CanFrame rx;
65

  
66

  
67
	c=u0rb;
68

  
69
	if (c==0x0D || c==0x0A){
70
		if (n>=2 && n<7)
71
			ipsnd_dtq (CanRx,(VP_INT) rx.msg);
72
		n=0;
73
		rx.data.id=rx.data.rtr=rx.data.val=0;
74
		return;
75
	}
76
	
77
	switch (n){
78
		case 0:rx.data.id=c; break;
79
		case 1:rx.data.rtr=c; break;
80
		case 2:
81
		case 3:
82
		case 4:
83
		case 5: if(c>='0' && c<='9') {
84
					rx.data.val=(rx.data.val<<4)+(c-'0');
85
					break;
86
				}
87
				c&=~32;
88
				if (c>='A' || c<='F') 
89
					rx.data.val=(rx.data.val<<4)+(10+(c-'A'));
90
				break;
91
	}
92
	n++;
93
}
94

  
95
char * ptx=NULL;
96

  
97
void uart0_itx(char str[])
98
{
99
	s0tic=3;
100
	ptx=str;
101
	u0tbl=*ptx++;	
102
}
103

  
104
void uart0_itx_ok(void)
105
{
106
	if (*ptx)
107
	{
108
		u0tbl=*ptx++;
109
	}
110
	else
111
	{
112
		iset_flg(ev_bus_fin_tr,(UINT) 1);
113
	}
114
}
115

  
116

  
trunk/tp_info6/Emb_App/periph.h
1

  
2
#define ADDR(x) ((x & ~0x20) - 'A')
3

  
4
int periph_read (char addr,int * val);
5
void periph_write (char addr,int valeur);
6
void periph_inter(char addr);
7
void iperiph_write (char addr,int valeur);
8
void iperiph_inter(char addr);
9
void periph_even(char addr);
10

  
11
static void int_2_hex(unsigned int val, char * str);
12

  
13
typedef union {	
14
	struct {
15
		unsigned char id;
16
		unsigned char rtr;
17
		unsigned int  val;
18
	}data;
19
	VP_INT  msg;
20
}CanFrame;
21

  
22
typedef struct {
23
	unsigned char maj;
24
	unsigned short val;
25
	UINT ev;
26
}Tperiph;
27

  
28
void periph_init(void);
29

  
30
extern Tperiph periph[26];
31
extern int canal[7];
32
extern int canal_ok;
trunk/tp_info6/Emb_App/uart0.h
1
// Header for uart0 control
2

  
3
void uart0_init(void);
4
void uart0_irx(void);
trunk/tp_info6/Emb_App/can.c
1
// subroutines for control ADC0 in one shot mode with sweep on channels 0 & 1
2

  
3
#ifdef M32C87
4
	#include "sfr32c87.h"
5
#endif
6

  
7
#ifdef M32C83
8
	#include "sfr32c83.h"
9
#endif
10

  
11
#if M32C87
12
// Carte M32C87 Cust GE
13
void can_init(void)
14
{
15
     pd0 = 0xE0;             		// pd10 (bit 7,6,5) configured for outputs
16
     pu00 = 0;                		// no pull up for inputs p0_3..p0_0
17
     ad0con0 = 0x18;           		// one shot sweep mode 0 Fad=Fosc/4
18
     ad0con1 = 0x28;           		// Vref connected resolution 10 bits
19
     ad0con2 = 0x05;           		// CAN connected on port 0 sample&hold active
20
	 ad0con3 = 0x00;				// no sweep mode on severals ports
21
	 ad0con4 = 0x00;				// no use for severals ports
22
	 adst_ad0con0 = 1;				// Run conversion
23
}
24
#endif
25

  
26
#ifdef M32C83
27
// Carte M32C83 LP
28
void can_init(void)
29
{
30
    pd10 = 0x00;                        //conversion sur voie 0 et 1 port 10 
31
    pur3 = 0x00;                        //pas de resistance de tirage
32
    ad0con2 = 0x01;                     //echantillonneur bloqueur actif
33
    ad0con1 = 0x38;                     //Vref connecte mode 10 bits
34
    ad0con0 = 0x18;                     //Fad/3 declenchement logiciel en mode balayage continu
35
    adst_ad0con0 = 1;                   //depart conversion
36
}
37
#endif
trunk/tp_info6/Emb_App/lcd.c
1
#ifdef M32C87
2
	#include "sfr32c87.h"
3
	#define LCD_RS p3_0
4
	#define LCD_RW p3_1
5
	#define LCD_E  p3_2
6

  
7
	#define LCD_DATA(x) p3= (x & 0xF0) | (p3 & 0x0F);
8
	#define dLCD_DATA pd3=0xF0 | pd3;
9

  
10
	#define dLCD_RS	pd3_0
11
	#define dLCD_RW	pd3_1
12
	#define dLCD_E	pd3_2	
13
#endif
14

  
15
#ifdef M32C83
16
	#include "sfr32c83.h"
17
	#define LCD_RS p3_0
18
	#define LCD_RW p3_1
19
	#define LCD_E  p3_2
20

  
21
	#define LCD_DATA(x) p3= x;
22
	#define dLCD_DATA pd3=0xFF;
23

  
24
	#define dLCD_RS	pd3_0
25
	#define dLCD_RW	pd3_1
26
	#define dLCD_E	pd3_2		
27
#endif
28

  
29
#include "lcd.h"
30

  
31

  
32
#ifdef M32C87
33
void lcd_car(char c)
34
{
35
	LCD_DATA (c);
36
    LCD_E=1;
37
    delay(10);
38
   	LCD_E=0;
39
   	delay(10);
40

  
41
   	LCD_DATA(c<<4);
42
    LCD_E=1;
43
   	delay(10);
44
    LCD_E=0;
45
   	delay(10);
46
}
47
#endif
48

  
49

  
50
#ifdef M32C83
51
void lcd_car(char c)
52
{
53
	LCD_DATA (c);
54
    LCD_E=1;
55
    delay(10);
56
   	LCD_E=0;
57
   	delay(10);
58
}
59
#endif
60

  
61

  
62

  
63
void lcd_com(char c)
64
{
65
   LCD_RS=0;
66
   lcd_car(c);
67
}
68

  
69

  
70
void lcd_putc(char c)
71
{
72
   LCD_RS=1;
73
   lcd_car(c);
74
}
75

  
76
void lcd_str(char far *p)
77
{
78
char c;
79
	while (c=*p++)
80
		lcd_putc(c);	
81
}
82

  
83
void lcd_cls(void)
84
{
85
	lcd_com(0x01);
86
	delay(100);
87
}
88

  
89

  
90
void lcd_init()
91
{
92

  
93
	dLCD_E=1;
94
	dLCD_RS=1;
95
	dLCD_RW=1;
96
	dLCD_DATA;
97

  
98
	LCD_RW=0;
99
	LCD_RS=0;
100
	LCD_E=0;
101

  
102
   lcd_com(0x33); //init 4 bit
103
   delay(5000);
104
   lcd_com(0x32); // reset 4 bits
105
   delay(100);
106
   lcd_com(0x28);
107
   delay(100);   
108
   lcd_com(0x28);
109
   delay(100);   
110
   lcd_com(0x06);
111
   delay(100);   
112
   lcd_com(0x0E);
113
   lcd_com(0x01);
114
   delay(100);   
115
   lcd_com(0x80);
116
   delay(100);   
117
}
118

  
119
void delay (int n)
120
{
121
int i;
122

  
123
	for  (i=0;i<n*60;i++);
124
}
trunk/tp_info6/Emb_App/can.h
1
// Header file for using ADC0
2

  
3
void can_init(void);
trunk/tp_info6/Emb_App/lcd.h
1

  
2

  
3
void lcd_com (char);
4
void lcd_putc(char);
5
void lcd_car(char);
6
void lcd_str(char  far *p);
7
void lcd_cls(void);
8
void lcd_init(void);
9

  
10
void delay (int n);
trunk/tp_info6/Emb_App/sfr32c83.h
1
/************************************************************************
2
*                                                                       *
3
*   file name   : definition of M32C/80's SFR                           *
4
*                                                                       *
5
*   Copyright, 2003 RENESAS TECHNOLOGY CORPORATION                      *
6
*                   AND RENESAS SOLUTIONS CORPORATION                   *
7
*                                                                       *
8
*   Version     : 1.01  ( 2002-06-28)                                   *
9
*                 1.02  ( 2002-07-09)                                   *
10
*                 1.03  ( 2002-09-19)                                   *
11
*                   change:                                             *
12
*                       delete same symbol name                         *
13
*                 1.04  ( 2003-10-15)                                   *
14
*                   change:                                             *
15
*                           pu32        pur3_addr.bit.b1                *
16
*                            -> pu32        pur3_addr.bit.b2            *
17
*                           pu33        pur3_addr.bit.b1                *
18
*                            -> pu33        pur3_addr.bit.b3            *
19
*                           pu34        pur3_addr.bit.b1                *
20
*                            -> pu34        pur3_addr.bit.b4            *
21
*                           pu35        pur3_addr.bit.b1                *
22
*                            -> pu35        pur3_addr.bit.b5            *
23
*                           pu36        pur3_addr.bit.b1                *
24
*                            -> pu36        pur3_addr.bit.b6            *
25
*                           pu37        pur3_addr.bit.b1                *
26
*                            -> pu37        pur3_addr.bit.b7            *
27
*                           pu42        pur4_addr.bit.b1                *
28
*                            -> pu42        pur4_addr.bit.b2            *
29
*                           pu43        pur4_addr.bit.b1                *
30
*                            -> pu43        pur4_addr.bit.b3            *
31
*                                                                       *
32
*************************************************************************/
33
/*
34
  note:
35
    This data is a freeware that SFR for M32C/80 groups is described.
36
    Renesas Technology Corporation and Renesas Solutions Corporation
37
    assumes no responsibility for any damage that occurred by this data. 
38
*/
39

  
40
/************************************************************************
41
*   declare SFR address                                                 *
42
************************************************************************/
43
#pragma ADDRESS     pm0_addr	0004H       /* Processor mode register 0 */
44
#pragma ADDRESS     pm1_addr	0005H       /* Processor mode register 1 */
45
#pragma ADDRESS     cm0_addr	0006H       /* System clock control register 0 */
46
#pragma ADDRESS     cm1_addr	0007H       /* System clock control register 1 */
47
#pragma ADDRESS     wcr_addr	0008H       /* Wait control register */
48
#pragma ADDRESS     aier_addr	0009H       /* Address match interrupt enable register */
49
#pragma ADDRESS     prcr_addr	000aH       /* Protect register */
50
#pragma ADDRESS     ds_addr		000bH       /* External data bus width control register */
51
#pragma ADDRESS     mcd_addr	000cH       /* Main clock division register */
52
#pragma ADDRESS     cm2_addr	000dH       /* Oscillation stop detect register */
53
#pragma ADDRESS     wdts_addr	000eH       /* Watchdog timer start register */
54
#pragma ADDRESS     wdc_addr	000fH       /* Watchdog timer control register */
55
#pragma ADDRESS     rmad0_addr	0010H       /* Address match interrupt register 0 */
56
#pragma ADDRESS     rmad1_addr	0014H       /* Address match interrupt register 1 */
57
#pragma ADDRESS     plv_addr	0017H       /* PLL VDC control register */
58
#pragma ADDRESS     rmad2_addr	0018H       /* Address match interrupt register 2 */
59
#pragma ADDRESS     vdc0_addr	001bH       /* VDC control register 0 */
60
#pragma ADDRESS     rmad3_addr	001cH       /* Address match interrupt register 3 */
61
#pragma ADDRESS		vdc1_addr	001fH		/* VDC control register 1 */
62
#pragma ADDRESS		eiad_addr	0020H		/* Emulator Exclusive Use Interrupt Register */
63
#pragma ADDRESS		eitd_addr	0023H		/* Emulator Exclusive Use Interrupt Distinction Register*/
64
#pragma ADDRESS		eprr_addr	0024H		/* Emulator Exclusive Use Protect Register*/
65
#pragma ADDRESS		emu_addr	0025H		/* Emulator Setting Register*/
66
#pragma ADDRESS		roa_addr	0030H		/* ROM Area Setting Register*/
67
#pragma ADDRESS		dba_addr	0031H		/* Debugging Monitor Setting Register*/
68
#pragma ADDRESS		exa0_addr	0032H		/* Expansion Area Setting Register 0*/
69
#pragma ADDRESS		exa1_addr	0033H		/* Expansion Area Setting Register 1*/
70
#pragma ADDRESS		exa2_addr	0034H		/* Expansion Area Setting Register 2*/
71
#pragma ADDRESS		exa3_addr	0035H		/* Expansion Area Setting Register 3*/
72
#pragma ADDRESS     dramcont_addr    0040H  /* DRAM control register */
73
#pragma ADDRESS     refcnt_addr	0041H       /* DRAM refresh interval set register */
74
#pragma ADDRESS		fmr2_addr	0055H		/* Flash Memory Control Register 2*/
75
#pragma ADDRESS		fmr1_addr	0056H		/* Flash Memory Control Register 2*/
76
#pragma ADDRESS     fmr0_addr	0057H       /* Flash memory control register 0 */
77
#pragma ADDRESS     dm0ic_addr	0068H       /* DMA0 interrupt control register */
78
#pragma ADDRESS     tb5ic_addr  0069H       /* Timer B5 interrupt register */
79
#pragma ADDRESS     dm2ic_addr  006aH       /* DMA2 interrupt register */
80
#pragma ADDRESS     s2ric_addr  006bH       /* UART2 receive/ack interrupt control register */
81
#pragma ADDRESS     ta0ic_addr  006cH       /* Timer A0 interrupt control register */
82
#pragma ADDRESS     s3ric_addr  006dH       /* UART3 receive/ack interrupt control register */
83
#pragma ADDRESS     ta2ic_addr  006eH       /* Timer A2 interrupt control register */
84
#pragma ADDRESS     s4ric_addr  006fH       /* UART4 receive/ack interrupt control register */
85
#pragma ADDRESS     ta4ic_addr  0070H       /* Timer A4 interrupt control register */
86
#pragma ADDRESS     bcn3ic_addr 0071H       /* Bus collision (UART3) interrupt control register */
87
#pragma ADDRESS		bcn0ic_addr 0071H		/* Bus collision (UART0) interrupt control register */
88
#pragma ADDRESS     s0ric_addr  0072H       /* UART0 receive interrupt control register */
89
#pragma ADDRESS     ad0ic_addr  0073H       /* A/D0 conversion interrupt control register */
90
#pragma ADDRESS     s1ric_addr  0074H       /* UART1 receive interrupt control register */
91
#pragma ADDRESS     iio0ic_addr 0075H       /* Intelligent I/O interrupt control register 0 */
92
#pragma ADDRESS     tb1ic_addr  0076H       /* Timer B1 interrupt control register */
93
#pragma ADDRESS     iio2ic_addr 0077H       /* Intelligent I/O interrupt control register 2 */
94
#pragma ADDRESS     tb3ic_addr  0078H       /* Timer B3 interrupt control register */
95
#pragma ADDRESS     iio4ic_addr 0079H       /* Intelligent I/O interrupt control register 4 */
96
#pragma ADDRESS     int5ic_addr 007aH       /* INT5~ interrupt control register */
97
#pragma ADDRESS     iio6ic_addr 007bH       /* Intelligent I/O interrupt control register 6 */
98
#pragma ADDRESS     int3ic_addr 007cH       /* INT3~ interrupt control register */
99
#pragma ADDRESS     iio8ic_addr 007dH       /* Intelligent I/O interrupt control register 8 */
100
#pragma ADDRESS     int1ic_addr 007eH       /* INT1~ interrupt control register */
101
#pragma ADDRESS     iio10ic_addr 007fH      /* Intelligent I/O interrupt control register 10 */
102
#pragma ADDRESS		can1ic_addr 007fH		/* CAN1 Interrupt Control Register*/
103
#pragma ADDRESS     iio11ic_addr 0081H      /* Intelligent I/O interrupt control register 11 */
104
#pragma ADDRESS		can2ic_addr 0081H		/* CAN2 Interrupt Control Register*/
105
#pragma ADDRESS     ad1ic_addr  0086H       /* A/D1 conversion interrupt control register */
106
#pragma ADDRESS     dm1ic_addr  0088H       /* DMA1 interrupt control register */
107
#pragma ADDRESS     s2tic_addr  0089H       /* UART2 transmit/nack interrupt control register */
108
#pragma ADDRESS     dm3ic_addr  008aH       /* DMA3 interrupt control register */
109
#pragma ADDRESS     s3tic_addr  008bH       /* UART3 transmit/nack interrupt control register */
110
#pragma ADDRESS     ta1ic_addr  008cH       /* Timer A1 interrupt control register */
111
#pragma ADDRESS     s4tic_addr  008dH       /* UART4 transmit/nack interrupt control register */
112
#pragma ADDRESS     ta3ic_addr  008eH       /* Timer A3 interrupt control register */
113
#pragma ADDRESS     bcn2ic_addr 008fH       /* Bus collision (UART2) interrupt control register */
114
#pragma ADDRESS     s0tic_addr  0090H       /* UART0 transmit interrupt control register */
115
#pragma ADDRESS     bcn4ic_addr 0091H       /* Bus collision (UART4) interrupt control register */
116
#pragma ADDRESS		bcn1ic_addr 0091H		/* Bus collision (UART1) interrupt control register*/
117
#pragma ADDRESS     s1tic_addr  0092H       /* UART1 transmit interrupt control register */
118
#pragma ADDRESS     kupic_addr  0093H       /* Key input interrupt control register */
119
#pragma ADDRESS     tb0ic_addr  0094H       /* Timer B0 interrupt control register */
120
#pragma ADDRESS     iio1ic_addr 0095H       /* Intelligent I/O interrupt control register 1 */
121
#pragma ADDRESS     tb2ic_addr  0096H       /* Timer B2 interrupt control register */
122
#pragma ADDRESS     iio3ic_addr 0097H       /* Intelligent I/O interrupt control register 3 */
123
#pragma ADDRESS     tb4ic_addr  0098H       /* Timer B4 interrupt control register */
124
#pragma ADDRESS     iio5ic_addr 0099H       /* Intelligent I/O interrupt control register 5 */
125
#pragma ADDRESS     int4ic_addr 009aH       /* INT4~ interrupt control register */
126
#pragma ADDRESS     iio7ic_addr 009bH       /* Intelligent I/O interrupt control register 7 */
127
#pragma ADDRESS     int2ic_addr 009cH       /* INT2~ interrupt control register */
128
#pragma ADDRESS     iio9ic_addr 009dH       /* Intelligent I/O interrupt control register 9 */
129
#pragma ADDRESS		can0ic_addr 009dH		/* CAN0 Interrupt Control Register*/
130
#pragma ADDRESS     int0ic_addr 009eH       /* INT0~ interrupt control register */
131
#pragma ADDRESS     rlvl_addr   009fH       /* Exit priority register */
132
#pragma ADDRESS     iio0ir_addr 00a0H       /* Interrupt request register 0 */
133
#pragma ADDRESS     iio1ir_addr 00a1H       /* Interrupt request register 1 */
134
#pragma ADDRESS     iio2ir_addr 00a2H       /* Interrupt request register 2 */
135
#pragma ADDRESS     iio3ir_addr 00a3H       /* Interrupt request register 3 */
136
#pragma ADDRESS     iio4ir_addr 00a4H       /* Interrupt request register 4 */
137
#pragma ADDRESS     iio5ir_addr 00a5H       /* Interrupt request register 5 */
138
#pragma ADDRESS     iio6ir_addr 00a6H       /* Interrupt request register 6 */
139
#pragma ADDRESS     iio7ir_addr 00a7H       /* Interrupt request register 7 */
140
#pragma ADDRESS     iio8ir_addr 00a8H       /* Interrupt request register 8 */
141
#pragma ADDRESS     iio9ir_addr 00a9H       /* Interrupt request register 9 */
142
#pragma ADDRESS     iio10ir_addr 00aaH      /* Interrupt request register 10 */
143
#pragma ADDRESS     iio11ir_addr 00abH      /* Interrupt request register 11 */
144
#pragma ADDRESS     iio0ie_addr 00b0H       /* Interrupt enable register 0 */
145
#pragma ADDRESS     iio1ie_addr 00b1H       /* Interrupt enable register 1 */
146
#pragma ADDRESS     iio2ie_addr 00b2H       /* Interrupt enable register 2 */
147
#pragma ADDRESS     iio3ie_addr 00b3H       /* Interrupt enable register 3 */
148
#pragma ADDRESS     iio4ie_addr 00b4H       /* Interrupt enable register 4 */
149
#pragma ADDRESS     iio5ie_addr 00b5H       /* Interrupt enable register 5 */
150
#pragma ADDRESS     iio6ie_addr 00b6H       /* Interrupt enable register 6 */
151
#pragma ADDRESS     iio7ie_addr 00b7H       /* Interrupt enable register 7 */
152
#pragma ADDRESS     iio8ie_addr 00b8H       /* Interrupt enable register 8 */
153
#pragma ADDRESS     iio9ie_addr 00b9H       /* Interrupt enable register 9 */
154
#pragma ADDRESS     iio10ie_addr 00baH      /* Interrupt enable register 10 */
155
#pragma ADDRESS     iio11ie_addr 00bbH      /* Interrupt enable register 11 */
156
#pragma ADDRESS     g0tm0_addr  00c0H       /* Group 0 time measurement register 0 */
157
#pragma ADDRESS     g0tm1_addr  00c2H       /* Group 0 time measurement register 1 */
158
#pragma ADDRESS     g0tm2_addr  00c4H       /* Group 0 time measurement register 2 */
159
#pragma ADDRESS     g0tm3_addr  00c6H       /* Group 0 time measurement register 3 */
160
#pragma ADDRESS     g0tm4_addr  00c8H       /* Group 0 time measurement register 4 */
161
#pragma ADDRESS     g0tm5_addr  00caH       /* Group 0 time measurement register 5 */
162
#pragma ADDRESS     g0tm6_addr  00ccH       /* Group 0 time measurement register 6 */
163
#pragma ADDRESS     g0tm7_addr  00ceH       /* Group 0 time measurement register 7 */
164
#pragma ADDRESS     g0po0_addr  00c0H       /* Group 0 waveform generate register 0 */
165
#pragma ADDRESS     g0po1_addr  00c2H       /* Group 0 waveform generate register 1 */
166
#pragma ADDRESS     g0po2_addr  00c4H       /* Group 0 waveform generate register 2 */
167
#pragma ADDRESS     g0po3_addr  00c6H       /* Group 0 waveform generate register 3 */
168
#pragma ADDRESS     g0po4_addr  00c8H       /* Group 0 waveform generate register 4 */
169
#pragma ADDRESS     g0po5_addr  00caH       /* Group 0 waveform generate register 5 */
170
#pragma ADDRESS     g0po6_addr  00ccH       /* Group 0 waveform generate register 6 */
171
#pragma ADDRESS     g0po7_addr  00ceH       /* Group 0 waveform generate register 7 */
172
#pragma ADDRESS     g0pocr0_addr 00d0H      /* Group 0 pulse output control register0 */
173
#pragma ADDRESS     g0pocr1_addr 00d1H      /* Group 0 pulse output control register1 */
174
#pragma ADDRESS     g0pocr2_addr 00d2H      /* Group 0 pulse output control register2 */
175
#pragma ADDRESS     g0pocr3_addr 00d3H      /* Group 0 pulse output control register3 */
176
#pragma ADDRESS     g0pocr4_addr 00d4H      /* Group 0 pulse output control register4 */
177
#pragma ADDRESS     g0pocr5_addr 00d5H      /* Group 0 pulse output control register5 */
178
#pragma ADDRESS     g0pocr6_addr 00d6H      /* Group 0 pulse output control register6 */
179
#pragma ADDRESS     g0pocr7_addr 00d7H      /* Group 0 pulse output control register7 */
180
#pragma ADDRESS     g0tmcr0_addr 00d8H      /* Group 0 time measuring control register0 */
181
#pragma ADDRESS     g0tmcr1_addr 00d9H      /* Group 0 time measuring control register1 */
182
#pragma ADDRESS     g0tmcr2_addr 00daH      /* Group 0 time measuring control register2 */
183
#pragma ADDRESS     g0tmcr3_addr 00dbH      /* Group 0 time measuring control register3 */
184
#pragma ADDRESS     g0tmcr4_addr 00dcH      /* Group 0 time measuring control register4 */
185
#pragma ADDRESS     g0tmcr5_addr 00ddH      /* Group 0 time measuring control register5 */
186
#pragma ADDRESS     g0tmcr6_addr 00deH      /* Group 0 time measuring control register6 */
187
#pragma ADDRESS     g0tmcr7_addr 00dfH      /* Group 0 time measuring control register7 */
188
#pragma ADDRESS     g0bt_addr   00e0H       /* Group 0 base timer register */
189
#pragma ADDRESS     g0bcr0_addr 00e2H       /* Group 0 base timer control register0 */
190
#pragma ADDRESS     g0bcr1_addr 00e3H       /* Group 0 base timer control register1 */
191
#pragma ADDRESS     g0tpr6_addr 00e4H       /* Group 0 priscale reload register6 */
192
#pragma ADDRESS     g0tpr7_addr 00e5H       /* Group 0 priscale reload register7 */
193
#pragma ADDRESS     g0fe_addr   00e6H       /* Group 0 function enable register */
194
#pragma ADDRESS     g0fs_addr   00e7H       /* Group 0 function select register */
195
#pragma ADDRESS     g0rb_addr   00e8H       /* Group 0 SI/O receive buffer register */
196
#pragma ADDRESS     g0tb_addr   00eaH       /* Group 0 SI/O transmitting buffer register */
197
#pragma ADDRESS     g0dr_addr   00eaH       /* Group 0 receive data register */
198
#pragma ADDRESS     g0ri_addr   00ecH       /* Group 0 receive input register */
199
#pragma ADDRESS     g0mr_addr   00edH       /* Group 0 SI/O communication control register */
200
#pragma ADDRESS     g0to_addr   00eeH       /* Group 0 transmit output register */
201
#pragma ADDRESS     g0cr_addr   00efH       /* Group 0 SI/O communication control register */
202
#pragma ADDRESS     g0cmp0_addr 00f0H       /* Group 0 data compare register 0 */
203
#pragma ADDRESS     g0cmp1_addr 00f1H       /* Group 0 data compare register 1 */
204
#pragma ADDRESS     g0cmp2_addr 00f2H       /* Group 0 data compare register 2 */
205
#pragma ADDRESS     g0cmp3_addr 00f3H       /* Group 0 data compare register 3 */
206
#pragma ADDRESS     g0msk0_addr 00f4H       /* Group 0 data mask register 0 */
207
#pragma ADDRESS     g0msk1_addr 00f5H       /* Group 0 data mask register 1 */
208
#pragma ADDRESS     g0rcrc_addr 00f8H       /* Group 0 receive CRC code register */
209
#pragma ADDRESS     g0tcrc_addr 00faH       /* Group 0 transmit CRC code register */
210
#pragma ADDRESS     g0emr_addr  00fcH       /* Group 0 SI/O expansion mode register */
211
#pragma ADDRESS     g0erc_addr  00fdH       /* Group 0 SI/O expansion receive control register */
212
#pragma ADDRESS     g0irf_addr  00feH       /* Group 0 SI/O special communication interrupt detect register */
213
#pragma ADDRESS     g0etc_addr  00ffH       /* Group 0 SI/O expansion transmit control register */
214
#pragma ADDRESS     g1tm0_addr  0100H       /* Group 1 time measurement register 0 */
215
#pragma ADDRESS		g1po0_addr	0100H		/* Group 1 waveform generate register 0 */
216
#pragma ADDRESS     g1tm1_addr  0102H       /* Group 1 time measurement register 1 */
217
#pragma ADDRESS		g1po1_addr	0102H		/* Group 1 waveform generate register 1 */
218
#pragma ADDRESS     g1tm2_addr  0104H       /* Group 1 time measurement register 2 */
219
#pragma ADDRESS		g1po2_addr	0104H		/* Group 1 waveform generate register 2 */
220
#pragma ADDRESS     g1tm3_addr  0106H       /* Group 1 time measurement register 3 */
221
#pragma ADDRESS		g1po3_addr	0106H		/* Group 1 waveform generate register 3 */
222
#pragma ADDRESS     g1tm4_addr  0108H       /* Group 1 time measurement register 4 */
223
#pragma ADDRESS		g1po4_addr	0108H		/* Group 1 waveform generate register 4 */
224
#pragma ADDRESS     g1tm5_addr  010aH       /* Group 1 time measurement register 5 */
225
#pragma ADDRESS		g1po5_addr	010aH		/* Group 1 waveform generate register 5 */
226
#pragma ADDRESS     g1tm6_addr  010cH       /* Group 1 time measurement register 6 */
227
#pragma ADDRESS		g1po6_addr	010cH		/* Group 1 waveform generate register 6 */
228
#pragma ADDRESS     g1tm7_addr  010eH       /* Group 1 time measurement register 7 */
229
#pragma ADDRESS		g1po7_addr	010eH		/* Group 1 waveform generate register 7 */
230
#pragma ADDRESS     g1pocr0_addr 0110H      /* Group 1 waveform generate control register 0 */
231
#pragma ADDRESS     g1pocr1_addr 0111H      /* Group 1 waveform generate control register 1 */
232
#pragma ADDRESS     g1pocr2_addr 0112H      /* Group 1 waveform generate control register 2 */
233
#pragma ADDRESS     g1pocr3_addr 0113H      /* Group 1 waveform generate control register 3 */
234
#pragma ADDRESS     g1pocr4_addr 0114H      /* Group 1 waveform generate control register 4 */
235
#pragma ADDRESS     g1pocr5_addr 0115H      /* Group 1 waveform generate control register 5 */
236
#pragma ADDRESS     g1pocr6_addr 0116H      /* Group 1 waveform generate control register 6 */
237
#pragma ADDRESS     g1pocr7_addr 0117H      /* Group 1 waveform generate control register 7 */
238
#pragma ADDRESS     g1tmcr0_addr 0118H      /* Group 1 time measurement control register 0 */
239
#pragma ADDRESS     g1tmcr1_addr 0119H      /* Group 1 time measurement control register 1 */
240
#pragma ADDRESS     g1tmcr2_addr 011aH      /* Group 1 time measurement control register 2 */
241
#pragma ADDRESS     g1tmcr3_addr 011bH      /* Group 1 time measurement control register 3 */
242
#pragma ADDRESS     g1tmcr4_addr 011cH      /* Group 1 time measurement control register 4 */
243
#pragma ADDRESS     g1tmcr5_addr 011dH      /* Group 1 time measurement control register 5 */
244
#pragma ADDRESS     g1tmcr6_addr 011eH      /* Group 1 time measurement control register 6 */
245
#pragma ADDRESS     g1tmcr7_addr 011fH      /* Group 1 time measurement control register 7 */
246
#pragma ADDRESS     g1bt_addr    0120H      /* Group 1 base timer register */
247
#pragma ADDRESS     g1bcr0_addr  0122H      /* Group 1 base timer control register 0 */
248
#pragma ADDRESS     g1bcr1_addr  0123H      /* Group 1 base timer control register 1 */
249
#pragma ADDRESS     g1tpr6_addr  0124H      /* Group 1 time measurement prescaler register 6 */
250
#pragma ADDRESS     g1tpr7_addr  0125H      /* Group 1 time measurement prescaler register 7 */
251
#pragma ADDRESS     g1fe_addr    0126H      /* Group 1 function enable register */
252
#pragma ADDRESS     g1fs_addr    0127H      /* Group 1 function select register */
253
#pragma ADDRESS     g1rb_addr    0128H      /* Group 1 SI/O communication buffer register */
254
#pragma ADDRESS     g1tb_addr    012aH      /* Group 1 SI/O transmiting data register */
255
#pragma ADDRESS     g1dr_addr    012aH      /* Group 1 receive data register */
256
#pragma ADDRESS     g1ri_addr    012cH      /* Group 1 receive input register */
257
#pragma ADDRESS     g1mr_addr    012dH      /* Group 1 SI/O communication mode register */
258
#pragma ADDRESS     g1to_addr    012eH      /* Group 1 transmit output register */
259
#pragma ADDRESS     g1cr_addr    012fH      /* Group 1 SI/O communication control register */
260
#pragma ADDRESS     g1cmp0_addr  0130H      /* Group 1 data compare register 0 */
261
#pragma ADDRESS     g1cmp1_addr  0131H      /* Group 1 data compare register 1 */
262
#pragma ADDRESS     g1cmp2_addr  0132H      /* Group 1 data compare register 2 */
263
#pragma ADDRESS     g1cmp3_addr  0133H      /* Group 1 data compare register 3 */
264
#pragma ADDRESS     g1msk0_addr  0134H      /* Group 1 data mask register 0 */
265
#pragma ADDRESS     g1msk1_addr  0135H      /* Group 1 data mask register 1 */
266
#pragma ADDRESS     g1rcrc_addr  0138H      /* Group 1 receive CRC code register */
267
#pragma ADDRESS     g1tcrc_addr  013aH      /* Group 1 transmit CRC code register */
268
#pragma ADDRESS     g1emr_addr   013cH      /* Group 1 SI/O expansion mode register */
269
#pragma ADDRESS     g1erc_addr   013dH      /* Group 1 SI/O expansion receive control register */
270
#pragma ADDRESS     g1irf_addr   013eH      /* Group 1 SI/O special communication interrupt detect register */
271
#pragma ADDRESS     g1etc_addr   013fH      /* Group 1 SI/O expansion transmit control register */
272
#pragma ADDRESS     g2po0_addr   0140H      /* Group 2 waveform generate register 0 */
273
#pragma ADDRESS     g2po1_addr   0142H      /* Group 2 waveform generate register 1 */
274
#pragma ADDRESS     g2po2_addr   0144H      /* Group 2 waveform generate register 2 */
275
#pragma ADDRESS     g2po3_addr   0146H      /* Group 2 waveform generate register 3 */
276
#pragma ADDRESS     g2po4_addr   0148H      /* Group 2 waveform generate register 4 */
277
#pragma ADDRESS     g2po5_addr   014aH      /* Group 2 waveform generate register 5 */
278
#pragma ADDRESS     g2po6_addr   014cH      /* Group 2 waveform generate register 6 */
279
#pragma ADDRESS     g2po7_addr   014eH      /* Group 2 waveform generate register 7 */
280
#pragma ADDRESS     g2pocr0_addr 0150H      /* Group 2 waveform generate control register 0 */
281
#pragma ADDRESS     g2pocr1_addr 0151H      /* Group 2 waveform generate control register 1 */
282
#pragma ADDRESS     g2pocr2_addr 0152H      /* Group 2 waveform generate control register 2 */
283
#pragma ADDRESS     g2pocr3_addr 0153H      /* Group 2 waveform generate control register 3 */
284
#pragma ADDRESS     g2pocr4_addr 0154H      /* Group 2 waveform generate control register 4 */
285
#pragma ADDRESS     g2pocr5_addr 0155H      /* Group 2 waveform generate control register 5 */
286
#pragma ADDRESS     g2pocr6_addr 0156H      /* Group 2 waveform generate control register 6 */
287
#pragma ADDRESS     g2pocr7_addr 0157H      /* Group 2 waveform generate control register 7 */
288
#pragma ADDRESS     g2bt_addr    0160H      /* Group 2 base timer register */
289
#pragma ADDRESS     g2bcr0_addr  0162H      /* Group 2 base timer control register 0 */
290
#pragma ADDRESS     g2bcr1_addr  0163H      /* Group 2 base timer control register 1 */
291
#pragma ADDRESS     btsr_addr    0164H      /* base timer start register */
292
#pragma ADDRESS     g2fe_addr    0166H      /* Group 2 function enable register */
293
#pragma ADDRESS     g2rtp_addr   0167H      /* Group 2 RTP output buffer register */
294
#pragma ADDRESS     g2mr_addr    016aH      /* Group 2 SI/O communication mode register */
295
#pragma ADDRESS     g2cr_addr    016bH      /* Group 2 SI/O communication control register */
296
#pragma ADDRESS     g2tb_addr    016cH      /* Group 2 SI/O transmit buffer register */
297
#pragma ADDRESS     g2rb_addr    016eH      /* Group 2 SI/O receive buffer register */
298
#pragma ADDRESS     iear_addr    0170H      /* Group 2 IEBus address register */
299
#pragma ADDRESS     iecr_addr    0172H      /* Group 2 IEBus control register */
300
#pragma ADDRESS     ietif_addr   0173H      /* Group 2 IEBus transmit interrupt cause detect register */
301
#pragma ADDRESS     ierif_addr   0174H      /* Group 2 IEBus receive interrupt cause detect register */
302
#pragma ADDRESS     ips_addr     0178H      /* Input function select register */
303
#pragma ADDRESS     g3mr_addr    017aH      /* Group 3 SI/O communication mode register */
304
#pragma ADDRESS     g3cr_addr    017bH      /* Group 3 SI/O communication control register */
305
#pragma ADDRESS     g3tb_addr    017cH      /* Group 3 SI/O transmit buffer register */
306
#pragma ADDRESS     g3rb_addr    017eH      /* Group 3 SI/O receive buffer register */
307
#pragma ADDRESS     g3po0_addr   0180H      /* Group 3 waveform generate register 0 */
308
#pragma ADDRESS     g3po1_addr   0182H      /* Group 3 waveform generate register 1 */
309
#pragma ADDRESS     g3po2_addr   0184H      /* Group 3 waveform generate register 2 */
310
#pragma ADDRESS     g3po3_addr   0186H      /* Group 3 waveform generate register 3 */
311
#pragma ADDRESS     g3po4_addr   0188H      /* Group 3 waveform generate register 4 */
312
#pragma ADDRESS     g3po5_addr   018aH      /* Group 3 waveform generate register 5 */
313
#pragma ADDRESS     g3po6_addr   018cH      /* Group 3 waveform generate register 6 */
314
#pragma ADDRESS     g3po7_addr   018eH      /* Group 3 waveform generate register 7 */
315
#pragma ADDRESS     g3pocr0_addr 0190H      /* Group 3 waveform generate control register 0 */
316
#pragma ADDRESS     g3pocr1_addr 0191H      /* Group 3 waveform generate control register 1 */
317
#pragma ADDRESS     g3pocr2_addr 0192H      /* Group 3 waveform generate control register 2 */
318
#pragma ADDRESS     g3pocr3_addr 0193H      /* Group 3 waveform generate control register 3 */
319
#pragma ADDRESS     g3pocr4_addr 0194H      /* Group 3 waveform generate control register 4 */
320
#pragma ADDRESS     g3pocr5_addr 0195H      /* Group 3 waveform generate control register 5 */
321
#pragma ADDRESS     g3pocr6_addr 0196H      /* Group 3 waveform generate control register 6 */
322
#pragma ADDRESS     g3pocr7_addr 0197H      /* Group 3 waveform generate control register 7 */
323
#pragma ADDRESS     g3mk4_addr   0198H      /* Group 3 waveform generate mask register 4 */
324
#pragma ADDRESS     g3mk5_addr   019aH      /* Group 3 waveform generate mask register 5 */
325
#pragma ADDRESS     g3mk6_addr   019cH      /* Group 3 waveform generate mask register 6 */
326
#pragma ADDRESS     g3mk7_addr   019eH      /* Group 3 waveform generate mask register 7 */
327
#pragma ADDRESS     g3bt_addr    01a0H      /* Group 3 base timer register */
328
#pragma ADDRESS     g3bcr0_addr  01a2H      /* Group 3 base timer control register 0 */
329
#pragma ADDRESS     g3bcr1_addr  01a3H      /* Group 3 base timer control register 1 */
330
#pragma ADDRESS     g3fe_addr    01a6H      /* Group 3 function enable register */
331
#pragma ADDRESS     g3rtp_addr   01a7H      /* Group 3 RTP output buffer register */
332
//#pragma ADDRESS		hdlc1_addr	 01abH		/* Group 3 high-speed HDLC Communication Control Register 1 */
333
#pragma ADDRESS     hdlc_addr    01acH      /* Group 3 high-speed HDLC communication control register */
334
#pragma ADDRESS     g3flg_addr   01adH      /* Group 3 high-speed HDLC communication register */
335
#pragma ADDRESS     hcnt_addr    01aeH      /* Group 3 high-speed HDLC transmit counter */
336
#pragma ADDRESS     hadr0_addr	 01b0H      /* Group 3 high-speed HDLC data compare register 0 */
337
#pragma ADDRESS     hmsk0_addr	 01b2H      /* Group 3 high-speed HDLC data mask register 0 */
338
#pragma ADDRESS     hadr1_addr	 01b4H      /* Group 3 high-speed HDLC data compare register 1 */
339
#pragma ADDRESS     hmsk1_addr	 01b6H      /* Group 3 high-speed HDLC data mask register 1 */
340
#pragma ADDRESS     hadr2_addr	 01b8H      /* Group 3 high-speed HDLC data compare register 2 */
341
#pragma ADDRESS     hmsk2_addr	 01baH      /* Group 3 high-speed HDLC data mask register 2 */
342
#pragma ADDRESS     hadr3_addr	 01bcH      /* Group 3 high-speed HDLC data compare register 3 */
343
#pragma ADDRESS     hmsk3_addr 	 01beH      /* Group 3 high-speed HDLC data mask register 3 */
344

  
345
#pragma ADDRESS     ad10_addr    01c0H      /* A/D1 register 0 */
346
#pragma ADDRESS     ad11_addr    01c2H      /* A/D1 register 1 */
347
#pragma ADDRESS     ad12_addr    01c4H      /* A/D1 register 2 */
348
#pragma ADDRESS     ad13_addr    01c6H      /* A/D1 register 3 */
349
#pragma ADDRESS     ad14_addr    01c8H      /* A/D1 register 4 */
350
#pragma ADDRESS     ad15_addr    01caH      /* A/D1 register 5 */
351
#pragma ADDRESS     ad16_addr    01ccH      /* A/D1 register 6 */
352
#pragma ADDRESS     ad17_addr    01ceH      /* A/D1 register 7 */
353
#pragma ADDRESS     ad1con2_addr 01d4H      /* A/D1 control register 2 */
354
#pragma ADDRESS     ad1con0_addr 01d6H      /* A/D1 control register 0 */
355
#pragma ADDRESS     ad1con1_addr 01d7H      /* A/D1 control register 1 */
356

  
357
#pragma ADDRESS		c0slot0_0_addr	01e0H	/* Can0 Messege Slot Buffer0 Data0 */
358
#pragma ADDRESS		c0slot0_1_addr	01e1H	/* Can0 Messege Slot Buffer0 Data1 */
359
#pragma ADDRESS		c0slot0_2_addr	01e2H	/* Can0 Messege Slot Buffer0 Data2 */
360
#pragma ADDRESS		c0slot0_3_addr	01e3H	/* Can0 Messege Slot Buffer0 Data3 */
361
#pragma ADDRESS		c0slot0_4_addr	01e4H	/* Can0 Messege Slot Buffer0 Data4 */
362
#pragma ADDRESS		c0slot0_5_addr	01e5H	/* Can0 Messege Slot Buffer0 Data5 */
363
#pragma ADDRESS		c0slot0_6_addr	01e6H	/* Can0 Messege Slot Buffer0 Data6 */
364
#pragma ADDRESS		c0slot0_7_addr	01e7H	/* Can0 Messege Slot Buffer0 Data7 */
365
#pragma ADDRESS		c0slot0_8_addr	01e8H	/* Can0 Messege Slot Buffer0 Data8 */
366
#pragma ADDRESS		c0slot0_9_addr	01e9H	/* Can0 Messege Slot Buffer0 Data9 */
367
#pragma ADDRESS		c0slot0_10_addr	01eaH	/* Can0 Messege Slot Buffer0 Data10 */
368
#pragma ADDRESS		c0slot0_11_addr	01ebH	/* Can0 Messege Slot Buffer0 Data11 */
369
#pragma ADDRESS		c0slot0_12_addr	01ecH	/* Can0 Messege Slot Buffer0 Data12 */
370
#pragma ADDRESS		c0slot0_13_addr	01edH	/* Can0 Messege Slot Buffer0 Data13 */
371
#pragma ADDRESS		c0slot0_14_addr	01eeH	/* Can0 Messege Slot Buffer0 Data14 */
... This diff was truncated because it exceeds the maximum size that can be displayed.

Also available in: Unified diff